summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorStefan Müller-Klieser <s.mueller-klieser@phytec.de>2019-10-22 16:54:36 (GMT)
committerStefan Müller-Klieser <s.mueller-klieser@phytec.de>2019-10-23 12:03:37 (GMT)
commita12a52a8e5a370a58206cbaaedfe42876cdb98ab (patch)
treef97ec3d962c6f0cc9df2ac590f1704c3942a57a8
parent1cf970bfb954f9b0148b7e9926a29d528b3336be (diff)
downloadmeta-phytec-a12a52a8e5a370a58206cbaaedfe42876cdb98ab.zip
meta-phytec-a12a52a8e5a370a58206cbaaedfe42876cdb98ab.tar.bz2
layer: add support for phyCORE-STM32MP1
This is the work of Dominique Vovard To add support for the phyCORE-STM32MP1 module to the OpenSTLinux distribution. Signed-off-by: Dominique Vovard <dominique.vovard@dv-consultant.com> Signed-off-by: Stefan Müller-Klieser <s.mueller-klieser@phytec.de>
-rw-r--r--classes/extlinuxconf-phycore-stm32mp.bbclass250
-rw-r--r--classes/extlinuxconf-stm32mp.bbclass249
-rw-r--r--conf/eula/LICENCE.broadcom_bcm43xx65
-rw-r--r--conf/eula/LICENCE.cypress139
-rw-r--r--conf/eula/ST_EULA_SLA97
-rw-r--r--conf/eula/Vivante_GPU_drivers-End_User_Software_License_Terms.txt23
-rw-r--r--conf/eula/en.SLA0048.txt19
l---------conf/eula/phycore-stm32mp1-11
-rw-r--r--conf/layer.conf2
-rw-r--r--conf/machine/include/gpu_vivante.inc47
-rw-r--r--conf/machine/include/phytec-machine-common-stm32mp.inc304
-rw-r--r--conf/machine/include/phytec-machine-extlinux-config-stm32mp.inc116
-rw-r--r--conf/machine/include/phytec-machine-features-stm32mp.inc54
-rw-r--r--conf/machine/include/phytec-machine-flashlayout-deleteall-stm32mp.inc65
-rw-r--r--conf/machine/include/phytec-machine-flashlayout-stm32mp.inc291
-rw-r--r--conf/machine/phycore-stm32mp1-1.conf93
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-bsp/alsa/alsa-state-stm32mp1.bbappend7
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-bsp/alsa/alsa-state-stm32mp1/asound-phycore-stm32mp1-1.conf12
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-bsp/alsa/alsa-state-stm32mp1/asound-phycore-stm32mp1-1.state1205
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp/0002-phycore-update.patch547
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp/0003-fix-emmc-pinmux-phycore-usage.patch13
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp/0004-fix-internal-eth-clk-pll4.patch25
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp_%.bbappend7
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp-extlinux.bb40
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp-extlinux/boot.scr.cmd44
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp/0009-ARM-v2018.11-stm32mp-r2-add-phycore-stm32mp1xx-alpha1-machine.patch4213
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp/README.HOW_TO.txt268
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp_2018.11.bbappend5
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-extended/m4projects/m4projects-stm32mp1.bbappend39
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/4.19.9/0065-ARM-stm32mp1-r0-rc1-add-phycore-stm32mp1xx-alpha1-machine.patch4297
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-06-rtc.config1
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-07-eeprom.config1
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-08-spi-nor.config2
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-09-audio.config3
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-10-peb-hdmi.config1
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-11-wifi-r8712u-support.config95
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-12-add-dp83867-phy-support.config1
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-13-add-pca953x-led-support.config4
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp_4.19.bbappend25
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-st/images/phytec-common-tools.inc8
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-st/images/st-image-core.bbappend1
-rw-r--r--dynamic-layers/stm-st-stm32mp/recipes-st/images/st-image-weston.bbappend1
-rw-r--r--recipes-devtools/spitest/spidev-test_git.bb21
-rw-r--r--scripts/envsetup.sh1438
44 files changed, 14139 insertions, 0 deletions
diff --git a/classes/extlinuxconf-phycore-stm32mp.bbclass b/classes/extlinuxconf-phycore-stm32mp.bbclass
new file mode 100644
index 0000000..4426e9a
--- /dev/null
+++ b/classes/extlinuxconf-phycore-stm32mp.bbclass
@@ -0,0 +1,250 @@
+# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+# Released under the MIT license (see COPYING.MIT for the terms)
+#
+# --------------------------------------------------------------------
+# Extract from openembedded-core 'uboot-extlinux-config.bbclass' class
+# --------------------------------------------------------------------
+# External variables:
+#
+# UBOOT_EXTLINUX_CONSOLE - Set to "console=ttyX" to change kernel boot
+# default console.
+# UBOOT_EXTLINUX_LABELS - A list of targets for the automatic config.
+# UBOOT_EXTLINUX_KERNEL_ARGS - Add additional kernel arguments.
+# UBOOT_EXTLINUX_KERNEL_IMAGE - Kernel image name.
+# UBOOT_EXTLINUX_FDTDIR - Device tree directory.
+# UBOOT_EXTLINUX_FDT - Device tree file.
+# UBOOT_EXTLINUX_INITRD - Indicates a list of filesystem images to
+# concatenate and use as an initrd (optional).
+# UBOOT_EXTLINUX_MENU_DESCRIPTION - Name to use as description.
+# UBOOT_EXTLINUX_ROOT - Root kernel cmdline.
+# UBOOT_EXTLINUX_TIMEOUT - Timeout before DEFAULT selection is made.
+# Measured in 1/10 of a second.
+# UBOOT_EXTLINUX_DEFAULT_LABEL - Target to be selected by default after
+# the timeout period
+#
+# If there's only one label system will boot automatically and menu won't be
+# created. If you want to use more than one labels, e.g linux and alternate,
+# use overrides to set menu description, console and others variables.
+#
+# --------------------------------------------------------------------
+# STM32MP specific implementation
+# --------------------------------------------------------------------
+# Append new mechanism to allow multi 'extlinux.conf' file generation.
+# - multiple targets case:
+# each 'extlinux.conf' file generated is created under specific path:
+# '${B}/<UBOOT_EXTLINUX_BOOTPREFIXES>extlinux/extlinux.conf'
+# - simple target case:
+# the 'extlinux.conf' file generated is created under default path:
+# '${B}/extlinux/extlinux.conf'
+#
+# New external variables added:
+# UBOOT_EXTLINUX_TARGETS - A list of targets for multi config file
+# generation
+# UBOOT_EXTLINUX_BOOTPREFIXES - Bootprefix used in uboot script to select
+# extlinux.conf file to use
+#
+# --------------------------------------------------------------------
+# Output example:
+# --------------------------------------------------------------------
+# Following 'extlinux.conf' files are generated under ${UBOOT_EXTLINUX_INSTALL_DIR}:
+# ${UBOOT_EXTLINUX_BOOTPREFIXES_${UBOOT_EXTLINUX_TARGETS}[0]}extlinux/extlinux.conf
+# ${UBOOT_EXTLINUX_BOOTPREFIXES_${UBOOT_EXTLINUX_TARGETS}[1]}extlinux/extlinux.conf
+#
+# File content (${UBOOT_EXTLINUX_BOOTPREFIXES_${UBOOT_EXTLINUX_TARGETS}[0]}extlinux/exlinux.conf):
+# menu title Select the boot mode
+# TIMEOUT ${UBOOT_EXTLINUX_TIMEOUT}
+# DEFAULT ${UBOOT_EXTLINUX_DEFAULT_LABEL_${UBOOT_EXTLINUX_TARGETS}[0]}
+# LABEL ${UBOOT_EXTLINUX_LABELS_${UBOOT_EXTLINUX_TARGETS}[0]}[0]
+# KERNEL ${UBOOT_EXTLINUX_KERNEL} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_KERNEL_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# FDT ${UBOOT_EXTLINUX_FDT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_FDT_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# APPEND ${UBOOT_EXTLINUX_ROOT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_ROOT_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# LABEL ${UBOOT_EXTLINUX_LABELS_${UBOOT_EXTLINUX_TARGETS}[0]}[1]
+# KERNEL ${UBOOT_EXTLINUX_KERNEL} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_KERNEL_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+# FDT ${UBOOT_EXTLINUX_FDT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_FDT_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+# APPEND ${UBOOT_EXTLINUX_ROOT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_ROOT_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+#
+# File content (${UBOOT_EXTLINUX_BOOTPREFIXES_${UBOOT_EXTLINUX_TARGETS}[0]}extlinux/exlinux.conf):
+# menu title Select the boot mode
+# TIMEOUT ${UBOOT_EXTLINUX_TIMEOUT}
+# DEFAULT ${UBOOT_EXTLINUX_DEFAULT_LABEL_${UBOOT_EXTLINUX_TARGETS}[1]}
+# LABEL ${UBOOT_EXTLINUX_LABELS_${UBOOT_EXTLINUX_TARGETS}[1]}[0]
+# KERNEL ${UBOOT_EXTLINUX_KERNEL} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_KERNEL_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# FDT ${UBOOT_EXTLINUX_FDT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_FDT_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# APPEND ${UBOOT_EXTLINUX_ROOT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_ROOT_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# LABEL ${UBOOT_EXTLINUX_LABELS_${UBOOT_EXTLINUX_TARGETS}[1]}[1]
+# KERNEL ${UBOOT_EXTLINUX_KERNEL} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_KERNEL_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+# FDT ${UBOOT_EXTLINUX_FDT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_FDT_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+# APPEND ${UBOOT_EXTLINUX_ROOT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_ROOT_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+# --------------------------------------------------------------------
+
+UBOOT_EXTLINUX_TARGETS ?= ""
+
+UBOOT_EXTLINUX_CONSOLE ??= "console=${console}"
+UBOOT_EXTLINUX_LABELS ??= "linux"
+UBOOT_EXTLINUX_FDT ??= ""
+UBOOT_EXTLINUX_FDTDIR ??= "../"
+UBOOT_EXTLINUX_KERNEL_IMAGE ?= "/${KERNEL_IMAGETYPE}"
+UBOOT_EXTLINUX_KERNEL_ARGS ?= "rootwait rw"
+UBOOT_EXTLINUX_TIMEOUT ?= "20"
+
+UBOOT_EXTLINUX_CONFIGURE_FILES ??= ""
+
+python update_extlinuxconf_targets() {
+ """
+ Append dynamically to UBOOT_EXTLINUX_TARGETS new target list generated from
+ config flag list (UBOOT_EXTLINUX_CONFIG_FLAGS) and supported devicetree list
+ for each flag (UBOOT_EXTLINUX_DEVICEFLAG_xxx)
+ """
+ import re
+
+ default_targets = d.getVar('UBOOT_EXTLINUX_CONFIGURED_TARGETS')
+ if not default_targets:
+ bb.fatal("UBOOT_EXTLINUX_CONFIGURED_TARGETS not defined, please update your config")
+ if not default_targets.strip():
+ bb.fatal("No UBOOT_EXTLINUX_CONFIGURED_TARGETS list defined, nothing to do")
+ bb.note('UBOOT_EXTLINUX_CONFIGURED_TARGETS: %s' % default_targets)
+
+ config_flags = d.getVar('UBOOT_EXTLINUX_CONFIG_FLAGS')
+ if not config_flags:
+ bb.fatal("UBOOT_EXTLINUX_CONFIG_FLAGS not defined, please update your config")
+ if not config_flags.strip():
+ bb.fatal("No UBOOT_EXTLINUX_CONFIG_FLAGS list defined, nothing to do")
+ bb.note('UBOOT_EXTLINUX_CONFIG_FLAGS: %s' % config_flags)
+
+ for config_label in config_flags.split():
+ bb.note('*** Loop for config_label: %s' % config_label)
+ devicetree_list = d.getVar('UBOOT_EXTLINUX_DEVICEFLAG_%s' % config_label) or ''
+ if devicetree_list is None:
+ continue
+ for devicetree in devicetree_list.split():
+ bb.note('*** Loop for devicetree: %s' % devicetree)
+ target_prefix = re.match('^phycore-stm32(.*)$', devicetree)
+ bb.note('>>> New target Prefix: %s' % target_prefix)
+ new_target = target_prefix.group(1) + '_' + config_label
+ bb.note('>>> New target label: %s' % new_target)
+ if not new_target in default_targets.split():
+ bb.note('Computed target: "%s" is not part of UBOOT_EXTLINUX_CONFIGURED_TARGETS: %s' % (new_target, default_targets))
+ bb.note('Target not append to UBOOT_EXTLINUX_TARGETS')
+ continue
+ # Append target to UBOOT_EXTLINUX_TARGETS list
+ d.appendVar('UBOOT_EXTLINUX_TARGETS', ' ' + new_target)
+ bb.note('>>> Append %s to UBOOT_EXTLINUX_TARGETS' % new_target)
+ bb.note('>>> UBOOT_EXTLINUX_TARGETS (updated): %s' % d.getVar('UBOOT_EXTLINUX_TARGETS'))
+}
+
+python do_create_multiextlinux_config() {
+ targets = d.getVar('UBOOT_EXTLINUX_TARGETS')
+ if not targets:
+ bb.fatal("UBOOT_EXTLINUX_TARGETS not defined, nothing to do")
+ if not targets.strip():
+ bb.fatal("No targets, nothing to do")
+
+ for target in targets.split():
+
+ localdata = bb.data.createCopy(d)
+ overrides = localdata.getVar('OVERRIDES')
+ if not overrides:
+ bb.fatal('OVERRIDES not defined')
+ localdata.setVar('OVERRIDES', target + ':' + overrides)
+ # Initialize labels from localdata to allow target override
+ labels = localdata.getVar('UBOOT_EXTLINUX_LABELS')
+ if not labels:
+ bb.fatal("UBOOT_EXTLINUX_LABELS not defined, nothing to do")
+ if not labels.strip():
+ bb.fatal("No labels, nothing to do")
+
+ # Initialize subdir for extlinux.conf file location
+ if len(targets.split()) > 1:
+ bootprefix = localdata.getVar('UBOOT_EXTLINUX_BOOTPREFIXES') or ""
+ subdir = bootprefix + 'extlinux'
+ else:
+ subdir = 'extlinux'
+
+ # Initialize config file
+ cfile = os.path.join(d.getVar('B'), subdir , 'extlinux.conf')
+
+ # Create extlinux folder
+ bb.utils.mkdirhier(os.path.dirname(cfile))
+
+ # ************************************************************
+ # Copy/Paste extract of 'do_create_extlinux_config()' function
+ # from openembedded-core 'uboot-extlinux-config.bbclass' class
+ # ************************************************************
+ try:
+ with open(cfile, 'w') as cfgfile:
+ cfgfile.write('# Generic Distro Configuration file generated by OpenEmbedded\n')
+
+ if len(labels.split()) > 1:
+ cfgfile.write('menu title Select the boot mode\n')
+
+ spashscreen_name = localdata.getVar('UBOOT_SPLASH_IMAGE')
+ if not spashscreen_name:
+ bb.warn('UBOOT_SPLASH_IMAGE not defined')
+ else:
+ cfgfile.write('MENU BACKGROUND ../%s.bmp\n' % (spashscreen_name))
+
+ timeout = localdata.getVar('UBOOT_EXTLINUX_TIMEOUT')
+ if timeout:
+ cfgfile.write('TIMEOUT %s\n' % (timeout))
+
+ if len(labels.split()) > 1:
+ default = localdata.getVar('UBOOT_EXTLINUX_DEFAULT_LABEL')
+ if default:
+ cfgfile.write('DEFAULT %s\n' % (default))
+
+ for label in labels.split():
+ # **********************************************
+ # Add localdata reset to fix var expansion issue
+ # **********************************************
+ localdata = bb.data.createCopy(d)
+
+ overrides = localdata.getVar('OVERRIDES')
+ if not overrides:
+ bb.fatal('OVERRIDES not defined')
+
+ localdata.setVar('OVERRIDES', label + ':' + overrides)
+
+ extlinux_console = localdata.getVar('UBOOT_EXTLINUX_CONSOLE')
+
+ menu_description = localdata.getVar('UBOOT_EXTLINUX_MENU_DESCRIPTION')
+ if not menu_description:
+ menu_description = label
+
+ bb.note('>>> New %s LABEL' % label)
+
+ root = localdata.getVar('UBOOT_EXTLINUX_ROOT')
+ if not root:
+ bb.fatal('UBOOT_EXTLINUX_ROOT not defined')
+
+ kernel_image = localdata.getVar('UBOOT_EXTLINUX_KERNEL_IMAGE')
+ fdtdir = localdata.getVar('UBOOT_EXTLINUX_FDTDIR')
+
+ fdt = localdata.getVar('UBOOT_EXTLINUX_FDT')
+
+ if fdt:
+ cfgfile.write('LABEL %s\n\tKERNEL %s\n\tFDT %s\n' %
+ (menu_description, kernel_image, fdt))
+ elif fdtdir:
+ cfgfile.write('LABEL %s\n\tKERNEL %s\n\tFDTDIR %s\n' %
+ (menu_description, kernel_image, fdtdir))
+ else:
+ cfgfile.write('LABEL %s\n\tKERNEL %s\n' % (menu_description, kernel_image))
+
+ kernel_args = localdata.getVar('UBOOT_EXTLINUX_KERNEL_ARGS')
+
+ initrd = localdata.getVar('UBOOT_EXTLINUX_INITRD')
+ if initrd:
+ cfgfile.write('\tINITRD %s\n'% initrd)
+
+ kernel_args = root + " " + kernel_args
+ cfgfile.write('\tAPPEND %s %s\n' % (kernel_args, extlinux_console))
+
+ except OSError:
+ bb.fatal('Unable to open %s' % (cfile))
+}
+addtask create_multiextlinux_config before do_compile
+
+do_create_multiextlinux_config[dirs] += "${B}"
+do_create_multiextlinux_config[cleandirs] += "${B}"
+do_create_multiextlinux_config[prefuncs] += "update_extlinuxconf_targets"
+do_create_multiextlinux_config[file-checksums] += "${UBOOT_EXTLINUX_CONFIGURE_FILES}"
diff --git a/classes/extlinuxconf-stm32mp.bbclass b/classes/extlinuxconf-stm32mp.bbclass
new file mode 100644
index 0000000..f9a5092
--- /dev/null
+++ b/classes/extlinuxconf-stm32mp.bbclass
@@ -0,0 +1,249 @@
+# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+# Released under the MIT license (see COPYING.MIT for the terms)
+#
+# --------------------------------------------------------------------
+# Extract from openembedded-core 'uboot-extlinux-config.bbclass' class
+# --------------------------------------------------------------------
+# External variables:
+#
+# UBOOT_EXTLINUX_CONSOLE - Set to "console=ttyX" to change kernel boot
+
+# default console.
+# UBOOT_EXTLINUX_LABELS - A list of targets for the automatic config.
+# UBOOT_EXTLINUX_KERNEL_ARGS - Add additional kernel arguments.
+# UBOOT_EXTLINUX_KERNEL_IMAGE - Kernel image name.
+# UBOOT_EXTLINUX_FDTDIR - Device tree directory.
+# UBOOT_EXTLINUX_FDT - Device tree file.
+# UBOOT_EXTLINUX_INITRD - Indicates a list of filesystem images to
+# concatenate and use as an initrd (optional).
+# UBOOT_EXTLINUX_MENU_DESCRIPTION - Name to use as description.
+# UBOOT_EXTLINUX_ROOT - Root kernel cmdline.
+# UBOOT_EXTLINUX_TIMEOUT - Timeout before DEFAULT selection is made.
+# Measured in 1/10 of a second.
+# UBOOT_EXTLINUX_DEFAULT_LABEL - Target to be selected by default after
+# the timeout period
+#
+# If there's only one label system will boot automatically and menu won't be
+# created. If you want to use more than one labels, e.g linux and alternate,
+# use overrides to set menu description, console and others variables.
+#
+# --------------------------------------------------------------------
+# STM32MP specific implementation
+# --------------------------------------------------------------------
+# Append new mechanism to allow multi 'extlinux.conf' file generation.
+# - multiple targets case:
+# each 'extlinux.conf' file generated is created under specific path:
+# '${B}/<UBOOT_EXTLINUX_BOOTPREFIXES>extlinux/extlinux.conf'
+# - simple target case:
+# the 'extlinux.conf' file generated is created under default path:
+# '${B}/extlinux/extlinux.conf'
+#
+# New external variables added:
+# UBOOT_EXTLINUX_TARGETS - A list of targets for multi config file
+# generation
+# UBOOT_EXTLINUX_BOOTPREFIXES - Bootprefix used in uboot script to select
+# extlinux.conf file to use
+#
+# --------------------------------------------------------------------
+# Output example:
+# --------------------------------------------------------------------
+# Following 'extlinux.conf' files are generated under ${UBOOT_EXTLINUX_INSTALL_DIR}:
+# ${UBOOT_EXTLINUX_BOOTPREFIXES_${UBOOT_EXTLINUX_TARGETS}[0]}extlinux/extlinux.conf
+# ${UBOOT_EXTLINUX_BOOTPREFIXES_${UBOOT_EXTLINUX_TARGETS}[1]}extlinux/extlinux.conf
+#
+# File content (${UBOOT_EXTLINUX_BOOTPREFIXES_${UBOOT_EXTLINUX_TARGETS}[0]}extlinux/exlinux.conf):
+# menu title Select the boot mode
+# TIMEOUT ${UBOOT_EXTLINUX_TIMEOUT}
+# DEFAULT ${UBOOT_EXTLINUX_DEFAULT_LABEL_${UBOOT_EXTLINUX_TARGETS}[0]}
+# LABEL ${UBOOT_EXTLINUX_LABELS_${UBOOT_EXTLINUX_TARGETS}[0]}[0]
+# KERNEL ${UBOOT_EXTLINUX_KERNEL} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_KERNEL_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# FDT ${UBOOT_EXTLINUX_FDT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_FDT_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# APPEND ${UBOOT_EXTLINUX_ROOT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_ROOT_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# LABEL ${UBOOT_EXTLINUX_LABELS_${UBOOT_EXTLINUX_TARGETS}[0]}[1]
+# KERNEL ${UBOOT_EXTLINUX_KERNEL} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_KERNEL_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+# FDT ${UBOOT_EXTLINUX_FDT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_FDT_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+# APPEND ${UBOOT_EXTLINUX_ROOT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_ROOT_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+#
+# File content (${UBOOT_EXTLINUX_BOOTPREFIXES_${UBOOT_EXTLINUX_TARGETS}[0]}extlinux/exlinux.conf):
+# menu title Select the boot mode
+# TIMEOUT ${UBOOT_EXTLINUX_TIMEOUT}
+# DEFAULT ${UBOOT_EXTLINUX_DEFAULT_LABEL_${UBOOT_EXTLINUX_TARGETS}[1]}
+# LABEL ${UBOOT_EXTLINUX_LABELS_${UBOOT_EXTLINUX_TARGETS}[1]}[0]
+# KERNEL ${UBOOT_EXTLINUX_KERNEL} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_KERNEL_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# FDT ${UBOOT_EXTLINUX_FDT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_FDT_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# APPEND ${UBOOT_EXTLINUX_ROOT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_ROOT_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# LABEL ${UBOOT_EXTLINUX_LABELS_${UBOOT_EXTLINUX_TARGETS}[1]}[1]
+# KERNEL ${UBOOT_EXTLINUX_KERNEL} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_KERNEL_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+# FDT ${UBOOT_EXTLINUX_FDT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_FDT_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+# APPEND ${UBOOT_EXTLINUX_ROOT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_ROOT_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+# --------------------------------------------------------------------
+
+UBOOT_EXTLINUX_TARGETS ?= ""
+
+UBOOT_EXTLINUX_CONSOLE ??= "console=${console}"
+UBOOT_EXTLINUX_LABELS ??= "linux"
+UBOOT_EXTLINUX_FDT ??= ""
+UBOOT_EXTLINUX_FDTDIR ??= "../"
+UBOOT_EXTLINUX_KERNEL_IMAGE ?= "/${KERNEL_IMAGETYPE}"
+UBOOT_EXTLINUX_KERNEL_ARGS ?= "rootwait rw"
+UBOOT_EXTLINUX_TIMEOUT ?= "20"
+
+UBOOT_EXTLINUX_CONFIGURE_FILES ??= ""
+
+python update_extlinuxconf_targets() {
+ """
+ Append dynamically to UBOOT_EXTLINUX_TARGETS new target list generated from
+ config flag list (UBOOT_EXTLINUX_CONFIG_FLAGS) and supported devicetree list
+ for each flag (UBOOT_EXTLINUX_DEVICEFLAG_xxx)
+ """
+ import re
+
+ default_targets = d.getVar('UBOOT_EXTLINUX_CONFIGURED_TARGETS')
+ if not default_targets:
+ bb.fatal("UBOOT_EXTLINUX_CONFIGURED_TARGETS not defined, please update your config")
+ if not default_targets.strip():
+ bb.fatal("No UBOOT_EXTLINUX_CONFIGURED_TARGETS list defined, nothing to do")
+ bb.note('UBOOT_EXTLINUX_CONFIGURED_TARGETS: %s' % default_targets)
+
+ config_flags = d.getVar('UBOOT_EXTLINUX_CONFIG_FLAGS')
+ if not config_flags:
+ bb.fatal("UBOOT_EXTLINUX_CONFIG_FLAGS not defined, please update your config")
+ if not config_flags.strip():
+ bb.fatal("No UBOOT_EXTLINUX_CONFIG_FLAGS list defined, nothing to do")
+ bb.note('UBOOT_EXTLINUX_CONFIG_FLAGS: %s' % config_flags)
+
+ for config_label in config_flags.split():
+ bb.note('*** Loop for config_label: %s' % config_label)
+ devicetree_list = d.getVar('UBOOT_EXTLINUX_DEVICEFLAG_%s' % config_label) or ''
+ if devicetree_list is None:
+ continue
+ for devicetree in devicetree_list.split():
+ bb.note('*** Loop for devicetree: %s' % devicetree)
+ target_prefix = re.match('phycore-stm32(.*)$', devicetree)
+ new_target = target_prefix.group(1) + '_' + config_label
+ bb.note('>>> New target label: %s' % new_target)
+ if not new_target in default_targets.split():
+ bb.note('Computed target: "%s" is not part of UBOOT_EXTLINUX_CONFIGURED_TARGETS: %s' % (new_target, default_targets))
+ bb.note('Target not append to UBOOT_EXTLINUX_TARGETS')
+ continue
+ # Append target to UBOOT_EXTLINUX_TARGETS list
+ d.appendVar('UBOOT_EXTLINUX_TARGETS', ' ' + new_target)
+ bb.note('>>> Append %s to UBOOT_EXTLINUX_TARGETS' % new_target)
+ bb.note('>>> UBOOT_EXTLINUX_TARGETS (updated): %s' % d.getVar('UBOOT_EXTLINUX_TARGETS'))
+}
+
+python do_create_multiextlinux_config() {
+ targets = d.getVar('UBOOT_EXTLINUX_TARGETS')
+ if not targets:
+ bb.fatal("UBOOT_EXTLINUX_TARGETS not defined, nothing to do")
+ if not targets.strip():
+ bb.fatal("No targets, nothing to do")
+
+ for target in targets.split():
+
+ localdata = bb.data.createCopy(d)
+ overrides = localdata.getVar('OVERRIDES')
+ if not overrides:
+ bb.fatal('OVERRIDES not defined')
+ localdata.setVar('OVERRIDES', target + ':' + overrides)
+
+ # Initialize labels from localdata to allow target override
+ labels = localdata.getVar('UBOOT_EXTLINUX_LABELS')
+ if not labels:
+ bb.fatal("UBOOT_EXTLINUX_LABELS not defined, nothing to do")
+ if not labels.strip():
+ bb.fatal("No labels, nothing to do")
+
+ # Initialize subdir for extlinux.conf file location
+ if len(targets.split()) > 1:
+ bootprefix = localdata.getVar('UBOOT_EXTLINUX_BOOTPREFIXES') or ""
+ subdir = bootprefix + 'extlinux'
+ else:
+ subdir = 'extlinux'
+
+ # Initialize config file
+ cfile = os.path.join(d.getVar('B'), subdir , 'extlinux.conf')
+
+ # Create extlinux folder
+ bb.utils.mkdirhier(os.path.dirname(cfile))
+
+ # ************************************************************
+ # Copy/Paste extract of 'do_create_extlinux_config()' function
+ # from openembedded-core 'uboot-extlinux-config.bbclass' class
+ # ************************************************************
+ try:
+ with open(cfile, 'w') as cfgfile:
+ cfgfile.write('# Generic Distro Configuration file generated by OpenEmbedded\n')
+
+ if len(labels.split()) > 1:
+ cfgfile.write('menu title Select the boot mode\n')
+
+ spashscreen_name = localdata.getVar('UBOOT_SPLASH_IMAGE')
+ if not spashscreen_name:
+ bb.warn('UBOOT_SPLASH_IMAGE not defined')
+ else:
+ cfgfile.write('MENU BACKGROUND ../%s.bmp\n' % (spashscreen_name))
+
+ timeout = localdata.getVar('UBOOT_EXTLINUX_TIMEOUT')
+ if timeout:
+ cfgfile.write('TIMEOUT %s\n' % (timeout))
+
+ if len(labels.split()) > 1:
+ default = localdata.getVar('UBOOT_EXTLINUX_DEFAULT_LABEL')
+ if default:
+ cfgfile.write('DEFAULT %s\n' % (default))
+
+ for label in labels.split():
+ # **********************************************
+ # Add localdata reset to fix var expansion issue
+ # **********************************************
+ localdata = bb.data.createCopy(d)
+
+ overrides = localdata.getVar('OVERRIDES')
+ if not overrides:
+ bb.fatal('OVERRIDES not defined')
+
+ localdata.setVar('OVERRIDES', label + ':' + overrides)
+
+ extlinux_console = localdata.getVar('UBOOT_EXTLINUX_CONSOLE')
+
+ menu_description = localdata.getVar('UBOOT_EXTLINUX_MENU_DESCRIPTION')
+ if not menu_description:
+ menu_description = label
+
+ root = localdata.getVar('UBOOT_EXTLINUX_ROOT')
+ if not root:
+ bb.fatal('UBOOT_EXTLINUX_ROOT not defined')
+
+ kernel_image = localdata.getVar('UBOOT_EXTLINUX_KERNEL_IMAGE')
+ fdtdir = localdata.getVar('UBOOT_EXTLINUX_FDTDIR')
+
+ fdt = localdata.getVar('UBOOT_EXTLINUX_FDT')
+
+ if fdt:
+ cfgfile.write('LABEL %s\n\tKERNEL %s\n\tFDT %s\n' %
+ (menu_description, kernel_image, fdt))
+ elif fdtdir:
+ cfgfile.write('LABEL %s\n\tKERNEL %s\n\tFDTDIR %s\n' %
+ (menu_description, kernel_image, fdtdir))
+ else:
+ cfgfile.write('LABEL %s\n\tKERNEL %s\n' % (menu_description, kernel_image))
+
+ kernel_args = localdata.getVar('UBOOT_EXTLINUX_KERNEL_ARGS')
+
+ initrd = localdata.getVar('UBOOT_EXTLINUX_INITRD')
+ if initrd:
+ cfgfile.write('\tINITRD %s\n'% initrd)
+
+ kernel_args = root + " " + kernel_args
+ cfgfile.write('\tAPPEND %s %s\n' % (kernel_args, extlinux_console))
+
+ except OSError:
+ bb.fatal('Unable to open %s' % (cfile))
+}
+addtask create_multiextlinux_config before do_compile
+
+do_create_multiextlinux_config[dirs] += "${B}"
+do_create_multiextlinux_config[cleandirs] += "${B}"
+do_create_multiextlinux_config[prefuncs] += "update_extlinuxconf_targets"
+do_create_multiextlinux_config[file-checksums] += "${UBOOT_EXTLINUX_CONFIGURE_FILES}"
diff --git a/conf/eula/LICENCE.broadcom_bcm43xx b/conf/eula/LICENCE.broadcom_bcm43xx
new file mode 100644
index 0000000..ff26fdd
--- /dev/null
+++ b/conf/eula/LICENCE.broadcom_bcm43xx
@@ -0,0 +1,65 @@
+SOFTWARE LICENSE AGREEMENT
+
+The accompanying software in binary code form (“Software”), is licensed to you,
+or, if you are accepting on behalf of an entity, the entity and its affiliates
+exercising rights hereunder (“Licensee”) subject to the terms of this software
+license agreement (“Agreement”), unless Licensee and Broadcom Corporation
+(“Broadcom”) execute a separate written software license agreement governing
+use of the Software. ANY USE, REPRODUCTION, OR DISTRIBUTION OF THE SOFTWARE
+CONSTITUTES LICENSEE’S ACCEPTANCE OF THIS AGREEMENT.
+
+1. License. Subject to the terms and conditions of this Agreement,
+Broadcom hereby grants to Licensee a limited, non-exclusive, non-transferable,
+royalty-free license: (i) to use and integrate the Software with any other
+software; and (ii) to reproduce and distribute the Software complete,
+unmodified, and as provided by Broadcom, solely for use with Broadcom
+proprietary integrated circuit product(s) sold by Broadcom with which the
+Software was designed to be used, or their successors.
+
+2. Restrictions. Licensee shall distribute Software with a copy of this
+Agreement. Licensee shall not remove, efface or obscure any copyright or
+trademark notices from the Software. Reproductions of the Broadcom copyright
+notice shall be included with each copy of the Software, except where such
+Software is embedded in a manner not readily accessible to the end user.
+Licensee shall not: (i) use, license, sell or otherwise distribute the Software
+except as provided in this Agreement; (ii) attempt to modify in any way,
+reverse engineer, decompile or disassemble any portion of the Software; or
+(iii) use the Software or other material in violation of any applicable law or
+regulation, including but not limited to any regulatory agency. This Agreement
+shall automatically terminate upon Licensee’s failure to comply with any of the
+terms of this Agreement. In such event, Licensee will destroy all copies of the
+Software and its component parts.
+
+3. Ownership. The Software is licensed and not sold. Title to and
+ownership of the Software, including all intellectual property rights thereto,
+and any portion thereof remain with Broadcom or its licensors. Licensee hereby
+covenants that it will not assert any claim that the Software created by or for
+Broadcom infringe any intellectual property right owned or controlled by
+Licensee.
+
+4. Disclaimer. THE SOFTWARE IS OFFERED “AS IS,” AND BROADCOM PROVIDES AND
+GRANTS AND LICENSEE RECEIVES NO SUPPORT AND NO WARRANTIES OF ANY KIND, EXPRESS
+OR IMPLIED, BY STATUTE, COMMUNICATION OR CONDUCT WITH LICENSEE, OR OTHERWISE.
+BROADCOM SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A SPECIFIC PURPOSE, OR NONINFRINGEMENT CONCERNING THE SOFTWARE OR
+ANY UPGRADES TO OR DOCUMENTATION FOR THE SOFTWARE. WITHOUT LIMITATION OF THE
+ABOVE, BROADCOM GRANTS NO WARRANTY THAT THE SOFTWARE IS ERROR-FREE OR WILL
+OPERATE WITHOUT INTERRUPTION, AND GRANTS NO WARRANTY REGARDING ITS USE OR THE
+RESULTS THEREFROM INCLUDING, WITHOUT LIMITATION, ITS CORRECTNESS, ACCURACY, OR
+RELIABILITY. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL BROADCOM
+OR ANY OF ITS LICENSORS HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND ON ANY THEORY
+OF LIABILITY, WHETHER FOR BREACH OF CONTRACT, TORT (INCLUDING NEGLIGENCE) OR
+OTHERWISE, ARISING OUT OF THIS AGREEMENT OR USE, REPRODUCTION, OR DISTRIBUTION
+OF THE SOFTWARE, INCLUDING BUT NOT LIMITED TO LOSS OF DATA AND LOSS OF PROFITS,
+EVEN IF SUCH PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THESE
+LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF ANY
+LIMITED REMEDY.
+
+5. Export Laws. LICENSEE UNDERSTANDS AND AGREES THAT THE SOFTWARE IS
+SUBJECT TO UNITED STATES AND OTHER APPLICABLE EXPORT-RELATED LAWS AND
+REGULATIONS AND THAT LICENSEE MAY NOT EXPORT, RE-EXPORT OR TRANSFER THE
+SOFTWARE OR ANY DIRECT PRODUCT OF THE SOFTWARE EXCEPT AS PERMITTED UNDER THOSE
+LAWS. WITHOUT LIMITING THE FOREGOING, EXPORT, RE-EXPORT, OR TRANSFER OF THE
+SOFTWARE TO CUBA, IRAN, NORTH KOREA, SUDAN, AND SYRIA IS PROHIBITED.
+
diff --git a/conf/eula/LICENCE.cypress b/conf/eula/LICENCE.cypress
new file mode 100644
index 0000000..b320f27
--- /dev/null
+++ b/conf/eula/LICENCE.cypress
@@ -0,0 +1,139 @@
+### CYPRESS WIRELESS CONNECTIVITY DEVICES
+### DRIVER END USER LICENSE AGREEMENT (SOURCE AND BINARY DISTRIBUTION)
+
+PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE
+DOWNLOADING, INSTALLING, OR USING THIS SOFTWARE, ANY ACCOMPANYING
+DOCUMENTATION, OR ANY UPDATES PROVIDED BY CYPRESS ("Software"). BY
+DOWNLOADING, INSTALLING, OR USING THE SOFTWARE, YOU ARE AGREEING TO BE BOUND
+BY THIS AGREEMENT. IF YOU DO NOT AGREE TO ALL OF THE TERMS OF THIS
+AGREEMENT, PROMPTLY RETURN AND DO NOT USE THE SOFTWARE. IF YOU HAVE
+PURCHASED THE SOFTWARE, YOUR RIGHT TO RETURN THE SOFTWARE EXPIRES 30 DAYS
+AFTER YOUR PURCHASE AND APPLIES ONLY TO THE ORIGINAL PURCHASER.
+
+Software Provided in Binary Code Form. This paragraph applies to any Software
+provided in binary code form. Subject to the terms and conditions of this
+Agreement, Cypress Semiconductor Corporation ("Cypress") grants you a
+non-exclusive, non-transferable license under its copyright rights in the
+Software to reproduce and distribute the Software in object code form only,
+solely for use in connection with Cypress integrated circuit products
+("Purpose").
+
+Software Provided in Source Code Form. This paragraph applies to any Software
+provided in source code form ("Cypress Source Code"). Subject to the terms and
+conditions of this Agreement, Cypress grants you a non-exclusive,
+non-transferable license under its copyright rights in the Cypress Source Code
+to reproduce, modify, compile, and distribute the Cypress Source Code (whether
+in source code form or as compiled into binary code form) solely for the
+Purpose. Cypress retains ownership of the Cypress Source Code and any compiled
+version thereof. Subject to Cypress' ownership of the underlying Cypress
+Source Code, you retain ownership of any modifications you make to the
+Cypress Source Code. You agree not to remove any Cypress copyright or other
+notices from the Cypress Source Code and any modifications thereof. Any
+reproduction, modification, translation, compilation, or representation of
+the Cypress Source Code except as permitted in this paragraph is prohibited
+without the express written permission of Cypress.
+
+Free and Open Source Software. Portions of the Software may be licensed under
+free and/or open source licenses such as the GNU General Public License
+("FOSS"). FOSS is subject to the applicable license agreement and not this
+Agreement. If you are entitled to receive the source code from Cypress for any
+FOSS included with the Software, either the source code will be included with
+the Software or you may obtain the source code at no charge from
+<http://www.cypress.com/go/opensource>. The applicable license terms will
+accompany each source code package. To review the license terms applicable to
+any FOSS for which Cypress is not required to provide you with source code,
+please see the Software's installation directory on your computer.
+
+Proprietary Rights. The Software, including all intellectual property rights
+therein, is and will remain the sole and exclusive property of Cypress or its
+suppliers. Except as otherwise expressly provided in this Agreement, you may
+not: (i) modify, adapt, or create derivative works based upon the Software;
+(ii) copy the Software; (iii) except and only to the extent explicitly
+permitted by applicable law despite this limitation, decompile, translate,
+reverse engineer, disassemble or otherwise reduce the Software to
+human-readable form; or (iv) use the Software other than for the Purpose.
+
+No Support. Cypress may, but is not required to, provide technical support for
+the Software.
+
+Term and Termination. This Agreement is effective until terminated, and either
+party may terminate this Agreement at any time with or without cause. Your
+license rights under this Agreement will terminate immediately without notice
+from Cypress if you fail to comply with any provision of this Agreement. Upon
+termination, you must destroy all copies of Software in your possession or
+control. Termination of this Agreement will not affect any licenses validly
+granted as of the termination date to any end users of the Software. The
+following paragraphs shall survive any termination of this Agreement: "Free and
+Open Source Software," "Proprietary Rights," "Compliance With Law,"
+"Disclaimer," "Limitation of Liability," and "General."
+
+Compliance With Law. Each party agrees to comply with all applicable laws,
+rules and regulations in connection with its activities under this Agreement.
+Without limiting the foregoing, the Software may be subject to export control
+laws and regulations of the United States and other countries. You agree to
+comply strictly with all such laws and regulations and acknowledge that you
+have the responsibility to obtain licenses to export, re-export, or import
+the Software.
+
+Disclaimer. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES
+NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THE SOFTWARE,
+INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the
+right to make changes to the Software without notice. Cypress does not assume
+any liability arising out of the application or use of Software or any
+product or circuit described in the Software. Cypress does not authorize its
+products for use as critical components in life-support systems where a
+malfunction or failure may reasonably be expected to result in significant
+injury to the user. The inclusion of Cypress' product in a life-support
+system or application implies that the manufacturer of such system or
+application assumes all risk of such use and in doing so indemnifies Cypress
+against all charges.
+
+Limitation of Liability. IN NO EVENT WILL CYPRESS OR ITS SUPPLIERS,
+RESELLERS, OR DISTRIBUTORS BE LIABLE FOR ANY LOST REVENUE, PROFIT, OR DATA,
+OR FOR SPECIAL, INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR PUNITIVE DAMAGES
+HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING OUT OF THE
+USE OF OR INABILITY TO USE THE SOFTWARE EVEN IF CYPRESS OR ITS SUPPLIERS,
+RESELLERS, OR DISTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH
+DAMAGES. IN NO EVENT SHALL CYPRESS' OR ITS SUPPLIERS' RESELLERS', OR
+DISTRIBUTORS' TOTAL LIABILITY TO YOU, WHETHER IN CONTRACT, TORT (INCLUDING
+NEGLIGENCE), OR OTHERWISE, EXCEED THE PRICE PAID BY YOU FOR THE SOFTWARE.
+THE FOREGOING LIMITATIONS SHALL APPLY EVEN IF THE ABOVE-STATED WARRANTY FAILS
+OF ITS ESSENTIAL PURPOSE. BECAUSE SOME STATES OR JURISDICTIONS DO NOT ALLOW
+LIMITATION OR EXCLUSION OF CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
+LIMITATION MAY NOT APPLY TO YOU.
+
+Restricted Rights. The Software under this Agreement is commercial computer
+software as that term is described in 48 C.F.R. 252.227-7014(a)(1). If
+acquired by or on behalf of a civilian agency, the U.S. Government acquires
+this commercial computer software and/or commercial computer software
+documentation subject to the terms of this Agreement as specified in 48
+C.F.R. 12.212 (Computer Software) and 12.211 (Technical Data) of the Federal
+Acquisition Regulations ("FAR") and its successors. If acquired by or on
+behalf of any agency within the Department of Defense ("DOD"), the U.S.
+Government acquires this commercial computer software and/or commercial
+computer software documentation subject to the terms of this Agreement as
+specified in 48 C.F.R. 227.7202-3 of the DOD FAR Supplement ("DFAR") and its
+successors.
+
+General. This Agreement will bind and inure to the benefit of each party's
+successors and assigns, provided that you may not assign or transfer this
+Agreement, in whole or in part, without Cypress' written consent. This
+Agreement shall be governed by and construed in accordance with the laws of
+the State of California, United States of America, as if performed wholly
+within the state and without giving effect to the principles of conflict of
+law. The parties consent to personal and exclusive jurisdiction of and venue
+in, the state and federal courts within Santa Clara County, California;
+provided however, that nothing in this Agreement will limit Cypress' right to
+bring legal action in any venue in order to protect or enforce its
+intellectual property rights. No failure of either party to exercise or
+enforce any of its rights under this Agreement will act as a waiver of such
+rights. If any portion hereof is found to be void or unenforceable, the
+remaining provisions of this Agreement shall remain in full force and
+effect. This Agreement is the complete and exclusive agreement between the
+parties with respect to the subject matter hereof, superseding and replacing
+any and all prior agreements, communications, and understandings (both
+written and oral) regarding such subject matter. Any notice to Cypress will
+be deemed effective when actually received and must be sent to Cypress
+Semiconductor Corporation, ATTN: Chief Legal Officer, 198 Champion Court, San
+Jose, CA 95134 USA.
diff --git a/conf/eula/ST_EULA_SLA b/conf/eula/ST_EULA_SLA
new file mode 100644
index 0000000..5fbc604
--- /dev/null
+++ b/conf/eula/ST_EULA_SLA
@@ -0,0 +1,97 @@
+SLA0048 Rev4/March 2018
+
+BY INSTALLING COPYING, DOWNLOADING, ACCESSING OR OTHERWISE USING THIS SOFTWARE PACKAGE OR ANY PART THEREOF (AND THE RELATED DOCUMENTATION) FROM STMICROELECTRONICS INTERNATIONAL N.V, SWISS BRANCH AND/OR ITS AFFILIATED COMPANIES (STMICROELECTRONICS), THE RECIPIENT, ON BEHALF OF HIMSELF OR HERSELF, OR ON BEHALF OF ANY ENTITY BY WHICH SUCH RECIPIENT IS EMPLOYED AND/OR ENGAGED AGREES TO BE BOUND BY THIS SOFTWARE PACKAGE LICENSE AGREEMENT.
+
+Under STMicroelectronics’ intellectual property rights and subject to applicable licensing terms for any third-party software incorporated in this software package and applicable Open Source Terms (as defined here below), the redistribution, reproduction and use in source and binary forms of the software package or any part thereof, with or without modification, are permitted provided that the following conditions are met:
+1. Redistribution of source code (modified or not) must retain any copyright notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form, except as embedded into microcontroller or microprocessor device manufactured by or for STMicroelectronics or a software update for such device, must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+3. Neither the name of STMicroelectronics nor the names of other contributors to this software package may be used to endorse or promote products derived from this software package or part thereof without specific written permission.
+4. This software package or any part thereof, including modifications and/or derivative works of this software package, must be used and execute solely and exclusively on or in combination with a microcontroller or a microprocessor devices manufactured by or for STMicroelectronics.
+5. No use, reproduction or redistribution of this software package partially or totally may be done in any manner that would subject this software package to any Open Source Terms (as defined below).
+6. Some portion of the software package may contain software subject to Open Source Terms (as defined below) applicable for each such portion (“Open Source Software”), as further specified in the software package. Such Open Source Software is supplied under the applicable Open Source Terms and is not subject to the terms and conditions of license hereunder. “Open Source Terms” shall mean any open source license which requires as part of distribution of software that the source code of such software is distributed therewith or otherwise made available, or open source license that substantially complies with the Open Source definition specified at www.opensource.org and any other comparable open source license such as for example GNU General Public License (GPL), Eclipse Public License (EPL), Apache Software License, BSD license and MIT license.
+7. This software package may also include third party software as expressly specified in the software package subject to specific license terms from such third parties. Such third party software is supplied under such specific license terms and is not subject to the terms and conditions of license hereunder. By installing copying, downloading, accessing or otherwise using this software package, the recipient agrees to be bound by such license terms with regard to such third party software.
+8. STMicroelectronics has no obligation to provide any maintenance, support or updates for the software package.
+9. The software package is and will remain the exclusive property of STMicroelectronics and its licensors. The recipient will not take any action that jeopardizes STMicroelectronics and its licensors' proprietary rights or acquire any rights in the software package, except the limited rights specified hereunder.
+10. The recipient shall comply with all applicable laws and regulations affecting the use of the software package or any part thereof including any applicable export control law or regulation.
+11. Redistribution and use of this software package partially or any part thereof other than as permitted under this license is void and will automatically terminate your rights under this license.
+
+THIS SOFTWARE PACKAGE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE PACKAGE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+EXCEPT AS EXPRESSLY PERMITTED HEREUNDER AND SUBJECT TO THE APPLICABLE LICENSING TERMS FOR ANY THIRD-PARTY SOFTWARE INCORPORATED IN THE SOFTWARE PACKAGE AND OPEN SOURCE TERMS AS APPLICABLE, NO LICENSE OR OTHER RIGHTS, WHETHER EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY RIGHTS OF STMICROELECTRONICS OR ANY THIRD PARTY.
+
+###############################################################################
+
+Vivante End User Software License Terms
+
+The following are the terms to be agreed to by end users of Vivante Software licensed herein:
+
+Copyright 2003-2017 Vivante Corporation, all rights reserved.
+
+Use, reproduction and redistribution of this software in binary form, without modification and solely for use in conjunction with STMicroelectronics semiconductor chips with the Linux operating system environment that contain Vivante Corporation’s technology, are permitted provided that the following conditions are met:
+
+* Redistributions must reproduce the above copyright notice, this list of conditions and the following disclaimers in the documentation and/or other materials provided with the distribution.
+
+* Neither the name nor trademarks of STMicroelectronics International N.V. nor any other STMicroelectronics company (nor Vivante Corporation unless permission is granted separately by Vivante Corporation) may be used to endorse or promote products derived from this software without specific prior written permission.
+
+* No reverse engineering, decompilation or disassembly of this software is permitted.
+
+* No use, reproduction or redistribution of this software may be done in any manner that may cause this software to be redistributed as part of the Linux kernel or in any other manner that would subject this software to the terms of the GNU General Public License, the GNU Lesser General Public License, or any other copyleft license.
+
+DISCLAIMERS:
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER(S) "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, ARE DISCLAIMED. IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. NOR ANY OTHER STMICROELECTRONICS COMPANY (NOR VIVANTE CORPORATION) BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+THE DELIVERY OF THIS SOFTWARE DOES NOT CONVEY ANY LICENSE, WHETHER EXPRESS OR IMPLIED, TO ANY THIRD-PARTY INTELLECTUAL PROPERTY RIGHTS.
+
+EXCEPT THE LIMITED RIGHT TO USE, REPRODUCE AND REDISTRIBUTE THIS SOFTWARE IN BINARY FORM, NO LICENSE OR OTHER RIGHTS, WHETHER EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY RIGHTS OF STMICROELECTRONICS INTERNATIONAL N.V. OR ANY OTHER STMICROELECTRONICS COMPANY (OR VIVANTE CORPORATION).
+
+
+###############################################################################
+
+### CYPRESS WIRELESS CONNECTIVITY DEVICES
+### DRIVER END USER LICENSE AGREEMENT (SOURCE AND BINARY DISTRIBUTION)
+
+PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE DOWNLOADING, INSTALLING, OR USING THIS SOFTWARE, ANY ACCOMPANYING DOCUMENTATION, OR ANY UPDATES PROVIDED BY CYPRESS ("Software"). BY DOWNLOADING, INSTALLING, OR USING THE SOFTWARE, YOU ARE AGREEING TO BE BOUND BY THIS AGREEMENT. IF YOU DO NOT AGREE TO ALL OF THE TERMS OF THIS AGREEMENT, PROMPTLY RETURN AND DO NOT USE THE SOFTWARE. IF YOU HAVE PURCHASED THE SOFTWARE, YOUR RIGHT TO RETURN THE SOFTWARE EXPIRES 30 DAYS AFTER YOUR PURCHASE AND APPLIES ONLY TO THE ORIGINAL PURCHASER.
+
+Software Provided in Binary Code Form. This paragraph applies to any Software provided in binary code form. Subject to the terms and conditions of this Agreement, Cypress Semiconductor Corporation ("Cypress") grants you a non-exclusive, non-transferable license under its copyright rights in the Software to reproduce and distribute the Software in object code form only, solely for use in connection with Cypress integrated circuit products ("Purpose").
+
+Software Provided in Source Code Form. This paragraph applies to any Software provided in source code form ("Cypress Source Code"). Subject to the terms and conditions of this Agreement, Cypress grants you a non-exclusive, non-transferable license under its copyright rights in the Cypress Source Code to reproduce, modify, compile, and distribute the Cypress Source Code (whether in source code form or as compiled into binary code form) solely for the Purpose. Cypress retains ownership of the Cypress Source Code and any compiled version thereof. Subject to Cypress' ownership of the underlying Cypress Source Code, you retain ownership of any modifications you make to the Cypress Source Code. You agree not to remove any Cypress copyright or other notices from the Cypress Source Code and any modifications thereof. Any reproduction, modification, translation, compilation, or representation of the Cypress Source Code except as permitted in this paragraph is prohibited without the express written permission of Cypress.
+
+Free and Open Source Software. Portions of the Software may be licensed under free and/or open source licenses such as the GNU General Public License ("FOSS"). FOSS is subject to the applicable license agreement and not this Agreement. If you are entitled to receive the source code from Cypress for any FOSS included with the Software, either the source code will be included with the Software or you may obtain the source code at no charge from <http://www.cypress.com/go/opensource>. The applicable license terms will accompany each source code package. To review the license terms applicable to any FOSS for which Cypress is not required to provide you with source code, please see the Software's installation directory on your computer.
+
+Proprietary Rights. The Software, including all intellectual property rights therein, is and will remain the sole and exclusive property of Cypress or its suppliers. Except as otherwise expressly provided in this Agreement, you may not: (i) modify, adapt, or create derivative works based upon the Software; (ii) copy the Software; (iii) except and only to the extent explicitly permitted by applicable law despite this limitation, decompile, translate, reverse engineer, disassemble or otherwise reduce the Software to human-readable form; or (iv) use the Software other than for the Purpose.
+
+No Support. Cypress may, but is not required to, provide technical support for the Software.
+
+Term and Termination. This Agreement is effective until terminated, and either party may terminate this Agreement at any time with or without cause. Your license rights under this Agreement will terminate immediately without notice from Cypress if you fail to comply with any provision of this Agreement. Upon termination, you must destroy all copies of Software in your possession or control. Termination of this Agreement will not affect any licenses validly granted as of the termination date to any end users of the Software. The following paragraphs shall survive any termination of this Agreement: "Free and Open Source Software," "Proprietary Rights," "Compliance With Law," "Disclaimer," "Limitation of Liability," and "General."
+
+Compliance With Law. Each party agrees to comply with all applicable laws, rules and regulations in connection with its activities under this Agreement. Without limiting the foregoing, the Software may be subject to export control laws and regulations of the United States and other countries. You agree to comply strictly with all such laws and regulations and acknowledge that you have the responsibility to obtain licenses to export, re-export, or import the Software.
+
+Disclaimer. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THE SOFTWARE, INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to the Software without notice. Cypress does not assume any liability arising out of the application or use of Software or any product or circuit described in the Software. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support system or application implies that the manufacturer of such system or application assumes all risk of such use and in doing so indemnifies Cypress against all charges.
+
+Limitation of Liability. IN NO EVENT WILL CYPRESS OR ITS SUPPLIERS, RESELLERS, OR DISTRIBUTORS BE LIABLE FOR ANY LOST REVENUE, PROFIT, OR DATA, OR FOR SPECIAL, INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR PUNITIVE DAMAGES HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING OUT OF THE USE OF OR INABILITY TO USE THE SOFTWARE EVEN IF CYPRESS OR ITS SUPPLIERS, RESELLERS, OR DISTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN NO EVENT SHALL CYPRESS' OR ITS SUPPLIERS' RESELLERS', OR DISTRIBUTORS' TOTAL LIABILITY TO YOU, WHETHER IN CONTRACT, TORT (INCLUDING NEGLIGENCE), OR OTHERWISE, EXCEED THE PRICE PAID BY YOU FOR THE SOFTWARE. THE FOREGOING LIMITATIONS SHALL APPLY EVEN IF THE ABOVE-STATED WARRANTY FAILS OF ITS ESSENTIAL PURPOSE. BECAUSE SOME STATES OR JURISDICTIONS DO NOT ALLOW LIMITATION OR EXCLUSION OF CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+
+Restricted Rights. The Software under this Agreement is commercial computer software as that term is described in 48 C.F.R. 252.227-7014(a)(1). If acquired by or on behalf of a civilian agency, the U.S. Government acquires this commercial computer software and/or commercial computer software documentation subject to the terms of this Agreement as specified in 48 C.F.R. 12.212 (Computer Software) and 12.211 (Technical Data) of the Federal Acquisition Regulations ("FAR") and its successors. If acquired by or on behalf of any agency within the Department of Defense ("DOD"), the U.S. Government acquires this commercial computer software and/or commercial computer software documentation subject to the terms of this Agreement as specified in 48 C.F.R. 227.7202-3 of the DOD FAR Supplement ("DFAR") and its successors.
+
+General. This Agreement will bind and inure to the benefit of each party's successors and assigns, provided that you may not assign or transfer this Agreement, in whole or in part, without Cypress' written consent. This Agreement shall be governed by and construed in accordance with the laws of the State of California, United States of America, as if performed wholly within the state and without giving effect to the principles of conflict of law. The parties consent to personal and exclusive jurisdiction of and venue in, the state and federal courts within Santa Clara County, California; provided however, that nothing in this Agreement will limit Cypress' right to bring legal action in any venue in order to protect or enforce its intellectual property rights. No failure of either party to exercise or enforce any of its rights under this Agreement will act as a waiver of such rights. If any portion hereof is found to be void or unenforceable, the remaining provisions of this Agreement shall remain in full force and effect. This Agreement is the complete and exclusive agreement between the parties with respect to the subject matter hereof, superseding and replacing any and all prior agreements, communications, and understandings (both written and oral) regarding such subject matter. Any notice to Cypress will be deemed effective when actually received and must be sent to Cypress Semiconductor Corporation, ATTN: Chief Legal Officer, 198 Champion Court, San
+Jose, CA 95134 USA.
+
+
+###############################################################################
+
+BROADCOM BCM43XX
+
+SOFTWARE LICENSE AGREEMENT
+
+The accompanying software in binary code form (“Software”), is licensed to you, or, if you are accepting on behalf of an entity, the entity and its affiliates exercising rights hereunder (“Licensee”) subject to the terms of this software license agreement (“Agreement”), unless Licensee and Broadcom Corporation (“Broadcom”) execute a separate written software license agreement governing use of the Software. ANY USE, REPRODUCTION, OR DISTRIBUTION OF THE SOFTWARE CONSTITUTES LICENSEE’S ACCEPTANCE OF THIS AGREEMENT.
+
+1. License. Subject to the terms and conditions of this Agreement, Broadcom hereby grants to Licensee a limited, non-exclusive, non-transferable, royalty-free license: (i) to use and integrate the Software with any other software; and (ii) to reproduce and distribute the Software complete, unmodified, and as provided by Broadcom, solely for use with Broadcom proprietary integrated circuit product(s) sold by Broadcom with which the Software was designed to be used, or their successors.
+
+2. Restrictions. Licensee shall distribute Software with a copy of this Agreement. Licensee shall not remove, efface or obscure any copyright or trademark notices from the Software. Reproductions of the Broadcom copyright notice shall be included with each copy of the Software, except where such Software is embedded in a manner not readily accessible to the end user.
+Licensee shall not: (i) use, license, sell or otherwise distribute the Software except as provided in this Agreement; (ii) attempt to modify in any way, reverse engineer, decompile or disassemble any portion of the Software; or (iii) use the Software or other material in violation of any applicable law or regulation, including but not limited to any regulatory agency. This Agreement shall automatically terminate upon Licensee’s failure to comply with any of the terms of this Agreement. In such event, Licensee will destroy all copies of the Software and its component parts.
+
+3. Ownership. The Software is licensed and not sold. Title to and ownership of the Software, including all intellectual property rights thereto, and any portion thereof remain with Broadcom or its licensors. Licensee hereby covenants that it will not assert any claim that the Software created by or for Broadcom infringe any intellectual property right owned or controlled by Licensee.
+
+4. Disclaimer. THE SOFTWARE IS OFFERED “AS IS,” AND BROADCOM PROVIDES AND GRANTS AND LICENSEE RECEIVES NO SUPPORT AND NO WARRANTIES OF ANY KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR CONDUCT WITH LICENSEE, OR OTHERWISE.
+BROADCOM SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A SPECIFIC PURPOSE, OR NONINFRINGEMENT CONCERNING THE SOFTWARE OR ANY UPGRADES TO OR DOCUMENTATION FOR THE SOFTWARE. WITHOUT LIMITATION OF THE ABOVE, BROADCOM GRANTS NO WARRANTY THAT THE SOFTWARE IS ERROR-FREE OR WILL OPERATE WITHOUT INTERRUPTION, AND GRANTS NO WARRANTY REGARDING ITS USE OR THE RESULTS THEREFROM INCLUDING, WITHOUT LIMITATION, ITS CORRECTNESS, ACCURACY, OR RELIABILITY. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL BROADCOM OR ANY OF ITS LICENSORS HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER FOR BREACH OF CONTRACT, TORT (INCLUDING NEGLIGENCE) OR OTHERWISE, ARISING OUT OF THIS AGREEMENT OR USE, REPRODUCTION, OR DISTRIBUTION OF THE SOFTWARE, INCLUDING BUT NOT LIMITED TO LOSS OF DATA AND LOSS OF PROFITS, EVEN IF SUCH PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY.
+
+5. Export Laws. LICENSEE UNDERSTANDS AND AGREES THAT THE SOFTWARE IS SUBJECT TO UNITED STATES AND OTHER APPLICABLE EXPORT-RELATED LAWS AND REGULATIONS AND THAT LICENSEE MAY NOT EXPORT, RE-EXPORT OR TRANSFER THE SOFTWARE OR ANY DIRECT PRODUCT OF THE SOFTWARE EXCEPT AS PERMITTED UNDER THOSE LAWS. WITHOUT LIMITING THE FOREGOING, EXPORT, RE-EXPORT, OR TRANSFER OF THE SOFTWARE TO CUBA, IRAN, NORTH KOREA, SUDAN, AND SYRIA IS PROHIBITED.
diff --git a/conf/eula/Vivante_GPU_drivers-End_User_Software_License_Terms.txt b/conf/eula/Vivante_GPU_drivers-End_User_Software_License_Terms.txt
new file mode 100644
index 0000000..8ae7919
--- /dev/null
+++ b/conf/eula/Vivante_GPU_drivers-End_User_Software_License_Terms.txt
@@ -0,0 +1,23 @@
+Vivante End User Software License Terms
+
+The following are the terms to be agreed to by end users of Vivante Software licensed herein:
+
+Copyright 2003-2017 Vivante Corporation, all rights reserved.
+
+Use, reproduction and redistribution of this software in binary form, without modification and solely for use in conjunction with STMicroelectronics semiconductor chips with the Linux operating system environment that contain Vivante Corporation’s technology, are permitted provided that the following conditions are met:
+
+* Redistributions must reproduce the above copyright notice, this list of conditions and the following disclaimers in the documentation and/or other materials provided with the distribution.
+
+* Neither the name nor trademarks of STMicroelectronics International N.V. nor any other STMicroelectronics company (nor Vivante Corporation unless permission is granted separately by Vivante Corporation) may be used to endorse or promote products derived from this software without specific prior written permission.
+
+* No reverse engineering, decompilation or disassembly of this software is permitted.
+
+* No use, reproduction or redistribution of this software may be done in any manner that may cause this software to be redistributed as part of the Linux kernel or in any other manner that would subject this software to the terms of the GNU General Public License, the GNU Lesser General Public License, or any other copyleft license.
+
+DISCLAIMERS:
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER(S) "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT, ARE DISCLAIMED. IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. NOR ANY OTHER STMICROELECTRONICS COMPANY (NOR VIVANTE CORPORATION) BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+THE DELIVERY OF THIS SOFTWARE DOES NOT CONVEY ANY LICENSE, WHETHER EXPRESS OR IMPLIED, TO ANY THIRD-PARTY INTELLECTUAL PROPERTY RIGHTS.
+
+EXCEPT THE LIMITED RIGHT TO USE, REPRODUCE AND REDISTRIBUTE THIS SOFTWARE IN BINARY FORM, NO LICENSE OR OTHER RIGHTS, WHETHER EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY RIGHTS OF STMICROELECTRONICS INTERNATIONAL N.V. OR ANY OTHER STMICROELECTRONICS COMPANY (OR VIVANTE CORPORATION).
diff --git a/conf/eula/en.SLA0048.txt b/conf/eula/en.SLA0048.txt
new file mode 100644
index 0000000..787de57
--- /dev/null
+++ b/conf/eula/en.SLA0048.txt
@@ -0,0 +1,19 @@
+SLA0048 Rev4/March 2018
+
+BY INSTALLING COPYING, DOWNLOADING, ACCESSING OR OTHERWISE USING THIS SOFTWARE PACKAGE OR ANY PART THEREOF (AND THE RELATED DOCUMENTATION) FROM STMICROELECTRONICS INTERNATIONAL N.V, SWISS BRANCH AND/OR ITS AFFILIATED COMPANIES (STMICROELECTRONICS), THE RECIPIENT, ON BEHALF OF HIMSELF OR HERSELF, OR ON BEHALF OF ANY ENTITY BY WHICH SUCH RECIPIENT IS EMPLOYED AND/OR ENGAGED AGREES TO BE BOUND BY THIS SOFTWARE PACKAGE LICENSE AGREEMENT.
+
+Under STMicroelectronics’ intellectual property rights and subject to applicable licensing terms for any third-party software incorporated in this software package and applicable Open Source Terms (as defined here below), the redistribution, reproduction and use in source and binary forms of the software package or any part thereof, with or without modification, are permitted provided that the following conditions are met:
+1. Redistribution of source code (modified or not) must retain any copyright notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form, except as embedded into microcontroller or microprocessor device manufactured by or for STMicroelectronics or a software update for such device, must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+3. Neither the name of STMicroelectronics nor the names of other contributors to this software package may be used to endorse or promote products derived from this software package or part thereof without specific written permission.
+4. This software package or any part thereof, including modifications and/or derivative works of this software package, must be used and execute solely and exclusively on or in combination with a microcontroller or a microprocessor devices manufactured by or for STMicroelectronics.
+5. No use, reproduction or redistribution of this software package partially or totally may be done in any manner that would subject this software package to any Open Source Terms (as defined below).
+6. Some portion of the software package may contain software subject to Open Source Terms (as defined below) applicable for each such portion (“Open Source Software”), as further specified in the software package. Such Open Source Software is supplied under the applicable Open Source Terms and is not subject to the terms and conditions of license hereunder. “Open Source Terms” shall mean any open source license which requires as part of distribution of software that the source code of such software is distributed therewith or otherwise made available, or open source license that substantially complies with the Open Source definition specified at www.opensource.org and any other comparable open source license such as for example GNU General Public License (GPL), Eclipse Public License (EPL), Apache Software License, BSD license and MIT license.
+7. This software package may also include third party software as expressly specified in the software package subject to specific license terms from such third parties. Such third party software is supplied under such specific license terms and is not subject to the terms and conditions of license hereunder. By installing copying, downloading, accessing or otherwise using this software package, the recipient agrees to be bound by such license terms with regard to such third party software.
+8. STMicroelectronics has no obligation to provide any maintenance, support or updates for the software package.
+9. The software package is and will remain the exclusive property of STMicroelectronics and its licensors. The recipient will not take any action that jeopardizes STMicroelectronics and its licensors' proprietary rights or acquire any rights in the software package, except the limited rights specified hereunder.
+10. The recipient shall comply with all applicable laws and regulations affecting the use of the software package or any part thereof including any applicable export control law or regulation.
+11. Redistribution and use of this software package partially or any part thereof other than as permitted under this license is void and will automatically terminate your rights under this license.
+
+THIS SOFTWARE PACKAGE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE PACKAGE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+EXCEPT AS EXPRESSLY PERMITTED HEREUNDER AND SUBJECT TO THE APPLICABLE LICENSING TERMS FOR ANY THIRD-PARTY SOFTWARE INCORPORATED IN THE SOFTWARE PACKAGE AND OPEN SOURCE TERMS AS APPLICABLE, NO LICENSE OR OTHER RIGHTS, WHETHER EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY RIGHTS OF STMICROELECTRONICS OR ANY THIRD PARTY.
diff --git a/conf/eula/phycore-stm32mp1-1 b/conf/eula/phycore-stm32mp1-1
new file mode 120000
index 0000000..ab103d9
--- /dev/null
+++ b/conf/eula/phycore-stm32mp1-1
@@ -0,0 +1 @@
+ST_EULA_SLA \ No newline at end of file
diff --git a/conf/layer.conf b/conf/layer.conf
index f5cf131..9268cc5 100644
--- a/conf/layer.conf
+++ b/conf/layer.conf
@@ -16,6 +16,8 @@ LAYERSERIES_COMPAT_phytec = "zeus"
# Additional license directories.
LICENSE_PATH += "${LAYERDIR}/licenses"
+PHYCORE_STM32MP_BASE = "${LAYERDIR}"
+
# Let us add layer-specific bbappends which are only applied when that
# layer is included in our configuration
BBFILES += "${@' '.join('${LAYERDIR}/dynamic-layers/%s/recipes*/*/*.bbappend' % layer \
diff --git a/conf/machine/include/gpu_vivante.inc b/conf/machine/include/gpu_vivante.inc
new file mode 100644
index 0000000..899124b
--- /dev/null
+++ b/conf/machine/include/gpu_vivante.inc
@@ -0,0 +1,47 @@
+# =========================================================================
+# GPU
+# =========================================================================
+GPU_USERLAND_LIBRARIES_WAYLAND ?= "gcnano-userland-multi-binary-stm32mp"
+GPU_USERLAND_LIBRARIES_EGLFS ?= "gcnano-userland-multi-binary-stm32mp"
+GPU_USERLAND_LIBRARIES_X11 ?= "mesa"
+
+# Helper function for overloading the default EGL/GLES implementation.
+# The Vivnate libraries are compatible with the Mesa headers
+# but we can have several backend available following the distro configuration:
+# - wayland
+# - x11
+# - wayland + x11
+# - framebuffer
+# - drm
+
+def get_gpu_vivante_handler(d):
+ """ Overloading the default EGL/GLES/mesa implementation."""
+ machine_features = d.getVar('MACHINE_FEATURES').split()
+ distro_features = d.getVar('DISTRO_FEATURES').split()
+
+ gpu_lib_wayland = d.getVar('GPU_USERLAND_LIBRARIES_WAYLAND').split()
+ gpu_lib_eglfs = d.getVar('GPU_USERLAND_LIBRARIES_EGLFS').split()
+ gpu_lib_x11 = d.getVar('GPU_USERLAND_LIBRARIES_X11').split()
+
+ if 'gpu' in machine_features:
+ if 'wayland' in distro_features:
+ provider = gpu_lib_wayland[0]
+ else:
+ if 'x11' in distro_features:
+ provider = gpu_lib_x11[0]
+ else:
+ '''no wayland, no X11 -> choose DRM/FB for eglfs'''
+ provider = gpu_lib_eglfs[0]
+ else:
+ provider = "mesa"
+
+ return provider;
+
+GPU_USERLAND_LIBRARIES_INSTALL = "${@get_gpu_vivante_handler(d)}"
+
+PREFERRED_PROVIDER_virtual/egl = "${@get_gpu_vivante_handler(d)}"
+PREFERRED_PROVIDER_virtual/libgles1 = "${@get_gpu_vivante_handler(d)}"
+PREFERRED_PROVIDER_virtual/libgles2 = "${@get_gpu_vivante_handler(d)}"
+PREFERRED_PROVIDER_virtual/libgbm = "${@get_gpu_vivante_handler(d)}"
+PREFERRED_PROVIDER_virtual/mesa = "${@bb.utils.contains('PREFERRED_PROVIDER_virtual/egl','mesa','mesa','mesa-gl',d)}"
+PREFERRED_PROVIDER_virtual/libgl = "${@bb.utils.contains('PREFERRED_PROVIDER_virtual/egl','mesa','mesa','mesa-gl',d)}"
diff --git a/conf/machine/include/phytec-machine-common-stm32mp.inc b/conf/machine/include/phytec-machine-common-stm32mp.inc
new file mode 100644
index 0000000..d539dfa
--- /dev/null
+++ b/conf/machine/include/phytec-machine-common-stm32mp.inc
@@ -0,0 +1,304 @@
+#@DESCRIPTION: Common Machine configuration for STM32 systems
+
+require conf/machine/include/phytec-machine-extlinux-config-stm32mp.inc
+require conf/machine/include/phytec-machine-features-stm32mp.inc
+require conf/machine/include/phytec-machine-flashlayout-stm32mp.inc
+require conf/machine/include/phytec-machine-flashlayout-deleteall-stm32mp.inc
+
+# Define specific common machine name
+MACHINEOVERRIDES .= ":stcommon"
+
+# Define specific common layer name
+MACHINEOVERRIDES .= ":stm32mpcommon"
+
+# =========================================================================
+# boot scheme
+# =========================================================================
+# List of supported boot schemes
+BOOTSCHEME_LABELS ??= "basic trusted optee"
+
+# =========================================================================
+# Machine settings
+# =========================================================================
+# Default machine feature
+MACHINE_FEATURES = "usbhost usbgadget alsa screen ext2"
+MACHINE_FEATURES_append = " ${@bb.utils.contains('BOOTSCHEME_LABELS', 'optee', 'optee', '', d)} "
+MACHINE_FEATURES_append = " tpm2 "
+
+# Default serial consoles (TTYs) to enable using getty
+# Before kernel 4.18, serial console are ttyS3 but after is ttySTM0
+SERIAL_CONSOLES = "115200;ttySTM0"
+SERIAL_CONSOLE = "115200 ttySTM0"
+
+# Don't include kernels in standard images
+RDEPENDS_${KERNEL_PACKAGE_NAME}-base = ""
+
+# Ship all kernel modules by default
+MACHINE_EXTRA_RRECOMMENDS = " kernel-modules"
+
+# Default device tree list supported per board
+STM32MP_DT_FILES_DK ??= ""
+STM32MP_DT_FILES_ED ??= ""
+STM32MP_DT_FILES_EV ??= ""
+STM32MP_DT_FILES_PHYCORE ??= ""
+# Set default supported device tree list
+STM32MP_DEVICETREE_append = " ${STM32MP_DT_FILES_DK} "
+STM32MP_DEVICETREE_append = " ${STM32MP_DT_FILES_ED} "
+STM32MP_DEVICETREE_append = " ${STM32MP_DT_FILES_EV} "
+STM32MP_DEVICETREE_append = " ${STM32MP_DT_FILES_PHYCORE} "
+
+# =========================================================================
+# Machine specific packages
+# =========================================================================
+MACHINE_EXTRA_RRECOMMENDS_append = " ${@bb.utils.contains('MACHINE_FEATURES', 'wifi', 'linux-firmware-bcm43430', '', d)} "
+MACHINE_EXTRA_RRECOMMENDS_append = " ${@bb.utils.contains('DISTRO_FEATURES','systemd',' wifi-suspend ','',d)} "
+MACHINE_EXTRA_RRECOMMENDS_append = " m4projects-stm32mp1 "
+MACHINE_EXTRA_RRECOMMENDS_append = " linux-examples-stm32mp1 "
+MACHINE_EXTRA_RRECOMMENDS_append = " m4fwcoredump "
+# Enable Software watchdog when sysvinit
+# We enable it to be aligned with the activation within u-boot https://gerrit.st.com/#/c/102528
+MACHINE_EXTRA_RRECOMMENDS_append = " ${@bb.utils.contains('DISTRO_FEATURES','sysvinit',' watchdog ','',d)} "
+
+# =========================================================================
+# Image
+# =========================================================================
+IMAGE_CLASSES += "image_types-stubi st-partitions-image"
+
+# Define image to use for extra partitions
+STM32MP_BOOTFS_IMAGE = "st-image-bootfs"
+STM32MP_BOOTFS_LABEL = "boot"
+STM32MP_BOOTFS_MOUNTPOINT_IMAGE = "/boot"
+STM32MP_USERFS_IMAGE = "st-image-userfs"
+STM32MP_USERFS_LABEL = "userfs"
+STM32MP_USERFS_MOUNTPOINT_IMAGE = "/usr/local"
+STM32MP_VENDORFS_IMAGE = "st-image-vendorfs"
+STM32MP_VENDORFS_LABEL = "vendorfs"
+STM32MP_VENDORFS_MOUNTPOINT_IMAGE = "/vendor"
+
+# Define extra partition to build
+PARTITIONS_IMAGE = "${STM32MP_BOOTFS_IMAGE} ${STM32MP_USERFS_IMAGE} ${STM32MP_VENDORFS_IMAGE}"
+PARTITIONS_MOUNTPOINT_IMAGE = "${STM32MP_BOOTFS_MOUNTPOINT_IMAGE} ${STM32MP_USERFS_MOUNTPOINT_IMAGE} ${STM32MP_VENDORFS_MOUNTPOINT_IMAGE}"
+
+# Enable licence summary and configure License content generation
+ENABLE_IMAGE_LICENSE_SUMMARY = "1"
+IMAGE_SUMMARY_LIST = "${STM32MP_BOOTFS_IMAGE}:${STM32MP_VENDORFS_IMAGE}:#IMAGE#:${STM32MP_USERFS_IMAGE}"
+
+# Provide list of partition to mount
+MOUNT_PARTITIONS_LIST = "${STM32MP_BOOTFS_LABEL},${STM32MP_BOOTFS_MOUNTPOINT_IMAGE}"
+MOUNT_PARTITIONS_LIST += "${STM32MP_USERFS_LABEL},${STM32MP_USERFS_MOUNTPOINT_IMAGE}"
+MOUNT_PARTITIONS_LIST += "${STM32MP_VENDORFS_LABEL},${STM32MP_VENDORFS_MOUNTPOINT_IMAGE}"
+
+# Define image partition size (supposed to be set as max size in image recipe)
+BOOTFS_PARTITION_SIZE = "65536"
+# New value proposed for rootfs is 768MB
+ROOTFS_PARTITION_SIZE = "768432"
+# If we consider the highest constraint is NAND size (so < 1GB)
+# Boot binaries 4 MB max (with optee) + bootfs 64 MB max + rootfs 768 MB max + userfs size (4*32MB) < 1024 MB
+USERFS_PARTITION_SIZE = "131072"
+# New value proposed for vendorfs is 16MB
+VENDORFS_PARTITION_SIZE = "16384"
+
+# Define volume list for multivolume UBIFS
+STM32MP_UBI_VOLUME += "${STM32MP_BOOTFS_IMAGE}-${DISTRO}-${MACHINE}:${BOOTFS_PARTITION_SIZE}"
+STM32MP_UBI_VOLUME += "${IMAGE_LINK_NAME}:${ROOTFS_PARTITION_SIZE}"
+STM32MP_UBI_VOLUME += "${STM32MP_VENDORFS_IMAGE}-${DISTRO}-${MACHINE}:${VENDORFS_PARTITION_SIZE}"
+STM32MP_UBI_VOLUME += "${STM32MP_USERFS_IMAGE}-${DISTRO}-${MACHINE}:${USERFS_PARTITION_SIZE}"
+
+# Set on machine side the max size for ROOTFS image to apply for default rootfs being built
+# On other image partition such settings is directly done in image recipe
+IMAGE_ROOTFS_MAXSIZE ?= "${ROOTFS_PARTITION_SIZE}"
+
+# ST Naming rules partitions for UBI format are :
+# nand_<PageSize>_<BlockSize>
+# nor_<BlockSize>
+# Like that a same UBI partition can be used for severals NAND/NOR providers
+
+# UBI Args for NAND soldered by default on MB1262
+# Micron MT29F8G16ABACAH4
+# LEB = BLOCK_SIZE - (2 * page size): 256*1024 - (2*4096)
+MKUBIFS_ARGS_nand_4_256 = "--min-io-size 4096 --leb-size 253952 --max-leb-cnt 4096 --space-fixup"
+UBINIZE_ARGS_nand_4_256 = "--min-io-size 4096 --peb-size 256KiB"
+
+# Define UBI labels to build
+MULTIUBI_BUILD_append = " nand_4_256 "
+
+# Set on machine side the UBI volume label for ROOTFS image to apply to reuse it
+# on kernel command line to mount UBI file system
+# On other image partition such settings is directly done in image recipe
+UBI_VOLNAME ?= "rootfs"
+
+# create minimal inode number (as it is done by default in image_types.bbclass)
+# add naming of ext4 FS to be aligned with gpt... scripts
+# For label name we are using IMAGE_NAME_SUFFIX we are removing "." and truncing to 16 caracters
+# -L new-volume-label
+# Set the volume label for the filesystem to new-volume-label. The maximum length of the volume label is 16 bytes.
+EXTRA_IMAGECMD_ext4 = "-i 4096 -L ${@d.getVar('IMAGE_NAME_SUFFIX').replace('.', '', 1)[:16]}"
+
+# Default FSTYPES requested
+IMAGE_FSTYPES = "tar.xz ext4"
+
+# Allow debug on the platform with gdb and openocd tools
+EXTRA_IMAGEDEPENDS_append = " \
+ gdb-cross-arm \
+ openocd-stm32mp-native \
+ sdcard-raw-tools-native \
+ "
+
+# Make sure to provide all expected tools in SDK
+ST_TOOLS_FOR_SDK = " \
+ nativesdk-gcc-arm-none-eabi \
+ nativesdk-binutils \
+ nativesdk-openocd-stm32mp \
+ nativesdk-sdcard-raw-tools \
+ nativesdk-ncurses-libncursesw \
+ nativesdk-perl-module-term-ansicolor \
+ nativesdk-perl-module-encode \
+ nativesdk-perl-module-encode-mime-header \
+ "
+# For support of string convertion (iconv) in SDK
+ST_TOOLS_FOR_SDK_append = " \
+ nativesdk-glibc-gconv-utf-16 \
+ nativesdk-glibc-gconv-utf-32 \
+ "
+
+# for populate_sdk, we will have all the tools
+TOOLCHAIN_HOST_TASK_append = " ${ST_TOOLS_FOR_SDK} "
+
+# Make sure to append mkimage to SDK for kernel uImage build
+TOOLCHAIN_HOST_TASK_append = " ${@bb.utils.contains('KERNEL_IMAGETYPE', 'uImage', 'nativesdk-u-boot-mkimage', '', d)} "
+TOOLCHAIN_HOST_TASK_append = " ${@bb.utils.contains('KERNEL_ALT_IMAGETYPE', 'uImage', 'nativesdk-u-boot-mkimage', '', d)} "
+# Make sure to append openssl to SDK for kernel-module and scripts build
+TOOLCHAIN_HOST_TASK_append = " nativesdk-openssl-dev "
+
+# Make sure to append bison to SDK for u-boot build
+TOOLCHAIN_HOST_TASK_append = " ${@bb.utils.contains('EXTRA_IMAGEDEPENDS', 'u-boot-stm32mp', 'nativesdk-bison', '', d)} "
+
+# for populate_sdk_ext, the tools are not desired as mandatory tools (aka basic
+# tools for devtool)
+TOOLCHAIN_HOST_TASK_remove_task-populate-sdk-ext = " ${ST_TOOLS_FOR_SDK} "
+
+# buildtools and uninatve are used only by populate_sdk_ext
+# populate_sdk_ext = buildtools + uninatve + layer
+# buildtools: sdk part of esdk (like sdk generated by populate_sdk)
+# uninative: basic tools for devtool
+TOOLCHAIN_HOST_TASK_append_pn-buildtools-tarball = " ${ST_TOOLS_FOR_SDK} "
+TOOLCHAIN_HOST_TASK_remove_pn-uninative-tarball = " ${ST_TOOLS_FOR_SDK} "
+
+# =========================================================================
+# Kernel
+# =========================================================================
+# Select kernel version
+PREFERRED_PROVIDER_virtual/kernel = "linux-stm32mp"
+
+# Kernel image type
+KERNEL_IMAGETYPE = "uImage"
+KERNEL_ALT_IMAGETYPE = " Image "
+KERNEL_ALT_IMAGETYPE =+ " vmlinux "
+KERNEL_ALT_IMAGETYPE =+ " zImage "
+
+# Maxsize authorized for uncompressed kernel binary
+# Define to null to skip kernel image size check
+KERNEL_IMAGE_MAXSIZE ?= ""
+
+# List of device tree to install
+KERNEL_DEVICETREE ?= "${STM32MP_KERNEL_DEVICETREE}"
+STM32MP_KERNEL_DEVICETREE += "${@' '.join('%s.dtb' % d for d in '${STM32MP_DEVICETREE}'.split())}"
+STM32MP_KERNEL_DEVICETREE += "${@' '.join('%s.dtb' % d for d in '${CUBE_M4_EXAMPLES_DT}'.split())}"
+STM32MP_KERNEL_DEVICETREE += "${@' '.join('%s.dtb' % d for d in '${LINUX_A7_EXAMPLES_DT}'.split())}"
+
+# Define the devicetree for Linux A7 examples
+LINUX_A7_EXAMPLES_DT ?= ""
+
+# =========================================================================
+# u-boot
+# =========================================================================
+EXTRA_IMAGEDEPENDS += "u-boot-stm32mp"
+
+# Define default U-Boot config
+UBOOT_CONFIG += "${@bb.utils.contains('BOOTSCHEME_LABELS', 'basic', 'basic', '', d)}"
+UBOOT_CONFIG += "${@bb.utils.contains('BOOTSCHEME_LABELS', 'trusted', 'trusted', '', d)}"
+UBOOT_CONFIG += "${@bb.utils.contains('BOOTSCHEME_LABELS', 'optee', 'optee', '', d)}"
+#Add this config until u-boot is able to flash with basic binary
+UBOOT_CONFIG += "${@bb.utils.contains('BOOTSCHEME_LABELS', 'basic', 'trusted', '', d)}"
+
+# Define u-boot defconfig and binary to use for each UBOOT_CONFIG
+UBOOT_CONFIG[basic] = "stm32mp15_basic_defconfig,,u-boot.img"
+UBOOT_CONFIG[trusted] = "stm32mp15_trusted_defconfig,,u-boot.stm32"
+UBOOT_CONFIG[optee] = "stm32mp15_optee_defconfig,,u-boot.stm32"
+
+# List of U-Boot device tree to use
+UBOOT_DEVICETREE = "${STM32MP_DEVICETREE}"
+
+# Define u-boot splashscreen file naming
+UBOOT_SPLASH_IMAGE = "splash"
+
+# =========================================================================
+# tf-a
+# =========================================================================
+# Finally we must compile tf-a in all cases as we need trusted binary to boot
+#EXTRA_IMAGEDEPENDS += "${@bb.utils.contains_any('BOOTSCHEME_LABELS', 'optee trusted', 'tf-a-stm32mp', '', d)}"
+EXTRA_IMAGEDEPENDS += "tf-a-stm32mp"
+
+# Define default TF-A config
+TF_A_CONFIG += "${@bb.utils.contains('BOOTSCHEME_LABELS', 'trusted', 'trusted', '', d)}"
+TF_A_CONFIG += "${@bb.utils.contains('BOOTSCHEME_LABELS', 'optee', 'optee', '', d)}"
+
+#Add this config until tf-a is able to flash with basic binary
+TF_A_CONFIG += "${@bb.utils.contains('BOOTSCHEME_LABELS', 'basic', 'trusted', '', d)}"
+#Add this config until optee is able to flash
+TF_A_CONFIG += "${@bb.utils.contains('BOOTSCHEME_LABELS', 'optee', 'trusted', '', d)}"
+
+# Define SECURE_PAYLOAD config to set for each TF_A_CONFIG
+TF_A_CONFIG_optee = "AARCH32_SP=optee"
+TF_A_CONFIG_trusted = "AARCH32_SP=sp_min"
+
+# List of TF-A device tree to use
+TF_A_DEVICETREE = "${STM32MP_DEVICETREE}"
+
+# =========================================================================
+# optee
+# =========================================================================
+# Map OPTEE configuration to device tree list
+OPTEE_CONF = "${STM32MP_DEVICETREE}"
+
+# =========================================================================
+# flashlayout
+# =========================================================================
+# Define bootscheme label to allow specific expansion for partition vars
+FLASHLAYOUT_BOOTSCHEME_LABELS += "${BOOTSCHEME_LABELS}"
+# Add specific scheme to provide flashlayout that will erase all storage devices
+FLASHLAYOUT_BOOTSCHEME_LABELS += "deleteall"
+
+# Default config labels supported
+FLASHLAYOUT_CONFIG_LABELS ??= ""
+
+# =========================================================================
+# Xserver
+# =========================================================================
+XSERVER ?= " \
+ xserver-xorg \
+ xserver-xorg-module-libint10 \
+ xf86-input-evdev \
+ xf86-video-modesetting \
+"
+
+# =========================================================================
+# Enable deploy of bootloader elf files
+# =========================================================================
+ELF_DEBUG_ENABLE = "1"
+
+# =========================================================================
+# M4 copro
+# =========================================================================
+# Define the devicetree for M4 examples
+CUBE_M4_EXAMPLES_DT ?= ""
+
+# Define the name of default copro firmware executed @boot time
+# This name is cherry picked from list defined in m4projects-stm32mp1.bb
+DEFAULT_COPRO_FIRMWARE = "OpenAMP_TTY_echo"
+
+# =========================================================================
+# GCNANO userland configuration
+# =========================================================================
+# Variable for using vendor directory instead of usr
+GCNANO_USERLAND_VENDOR_DIR = "${STM32MP_VENDORFS_MOUNTPOINT_IMAGE}"
diff --git a/conf/machine/include/phytec-machine-extlinux-config-stm32mp.inc b/conf/machine/include/phytec-machine-extlinux-config-stm32mp.inc
new file mode 100644
index 0000000..207565c
--- /dev/null
+++ b/conf/machine/include/phytec-machine-extlinux-config-stm32mp.inc
@@ -0,0 +1,116 @@
+#@DESCRIPTION: STM32MP machine extlinux file configuration
+
+# Set configuration file to monitor
+UBOOT_EXTLINUX_CONFIGURE_FILES_append = " ${PHYCORE_STM32MP_BASE}/conf/machine/include/phytec-machine-extlinux-config-stm32mp.inc:True "
+
+# Define the config flags to use to generate all extlinux targets
+UBOOT_EXTLINUX_CONFIG_FLAGS += "${@bb.utils.contains('FLASHLAYOUT_CONFIG_LABELS', 'emmc', '%s' % bb.utils.contains('BOOTSCHEME_LABELS', 'optee', 'emmc emmc-optee', 'emmc', d), '', d)}"
+UBOOT_EXTLINUX_CONFIG_FLAGS += "${@bb.utils.contains_any('FLASHLAYOUT_CONFIG_LABELS', [ 'nand-4-256', 'nor-nand-4-256' ], 'nand', '', d)}"
+UBOOT_EXTLINUX_CONFIG_FLAGS += "${@bb.utils.contains('FLASHLAYOUT_CONFIG_LABELS', 'nor-emmc', 'nor-emmc', '', d)}"
+UBOOT_EXTLINUX_CONFIG_FLAGS += "${@bb.utils.contains('FLASHLAYOUT_CONFIG_LABELS', 'nor-sdcard', 'nor-sdcard', '', d)}"
+UBOOT_EXTLINUX_CONFIG_FLAGS += "${@bb.utils.contains('FLASHLAYOUT_CONFIG_LABELS', 'sdcard', '%s' % bb.utils.contains('BOOTSCHEME_LABELS', 'optee', 'sdcard nor-emmc', 'sdcard', d), '', d)}"
+
+# Provide the list of supported devicetree for each config flag
+UBOOT_EXTLINUX_DEVICEFLAG_emmc ?= "${STM32MP_DT_FILES_PHYCORE}"
+UBOOT_EXTLINUX_DEVICEFLAG_emmc-optee ?= "${STM32MP_DT_FILES_PHYCORE}"
+UBOOT_EXTLINUX_DEVICEFLAG_nand ?= "${STM32MP_DT_FILES_PHYCORE}"
+UBOOT_EXTLINUX_DEVICEFLAG_nor-emmc ?= "${STM32MP_DT_FILES_PHYCORE}"
+UBOOT_EXTLINUX_DEVICEFLAG_nor-sdcard ?= "${STM32MP_DT_FILES_PHYCRE}"
+UBOOT_EXTLINUX_DEVICEFLAG_sdcard ?= "${STM32MP_DT_FILES_PHYCORE}"
+UBOOT_EXTLINUX_DEVICEFLAG_nor-emmc ?= "${STM32MP_DT_FILES_PHYCORE}"
+
+# Set generic extlinux bootdevice variable to ease definition
+EXTLINUX_BOOTDEVICE_EMMC = "mmc1"
+EXTLINUX_BOOTDEVICE_SDCARD = "mmc0"
+EXTLINUX_BOOTDEVICE_NORSDCARD = "nor0"
+EXTLINUX_BOOTDEVICE_NOREMMC = "nor0-mmc1"
+EXTLINUX_BOOTDEVICE_NAND = "nand0"
+
+# Set generic extlinux root variable to ease definition
+EXTLINUX_ROOT_EMMC = "root=/dev/mmcblk1p4"
+EXTLINUX_ROOT_EMMC_OPTEE = "root=/dev/mmcblk1p7"
+EXTLINUX_ROOT_NAND = "ubi.mtd=UBI rootfstype=ubifs root=ubi0:rootfs"
+EXTLINUX_ROOT_NOREMMC = "root=/dev/mmcblk1p3"
+EXTLINUX_ROOT_NORSDCARD = "root=/dev/mmcblk0p3"
+EXTLINUX_ROOT_SDCARD = "root=/dev/mmcblk0p6"
+
+# -----------------------------------------------------------------------------
+# REMINDER: how 'exlinux.conf' files are built
+#
+# The 'extlinux.conf' files are generated under ${UBOOT_EXTLINUX_INSTALL_DIR}:
+# ${UBOOT_EXTLINUX_INSTALL_DIR}/${UBOOT_EXTLINUX_BOOTPREFIXES_${UBOOT_EXTLINUX_TARGETS}[0]}extlinux/extlinux.conf
+# ${UBOOT_EXTLINUX_INSTALL_DIR}/${UBOOT_EXTLINUX_BOOTPREFIXES_${UBOOT_EXTLINUX_TARGETS}[1]}extlinux/extlinux.conf
+# ...
+#
+# File content (${UBOOT_EXTLINUX_BOOTPREFIXES_${UBOOT_EXTLINUX_TARGETS}[0]}extlinux/exlinux.conf):
+# menu title Select the boot mode
+# TIMEOUT ${UBOOT_EXTLINUX_TIMEOUT}
+# DEFAULT ${UBOOT_EXTLINUX_DEFAULT_LABEL_${UBOOT_EXTLINUX_TARGETS}[0]}
+# LABEL ${UBOOT_EXTLINUX_LABELS_${UBOOT_EXTLINUX_TARGETS}[0]}[0]
+# KERNEL ${UBOOT_EXTLINUX_KERNEL} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_KERNEL_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# FDT ${UBOOT_EXTLINUX_FDT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_FDT_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# APPEND ${UBOOT_EXTLINUX_ROOT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_ROOT_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# LABEL ${UBOOT_EXTLINUX_LABELS_${UBOOT_EXTLINUX_TARGETS}[0]}[1]
+# KERNEL ${UBOOT_EXTLINUX_KERNEL} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_KERNEL_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+# FDT ${UBOOT_EXTLINUX_FDT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_FDT_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+# APPEND ${UBOOT_EXTLINUX_ROOT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_ROOT_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+#
+# File content (${UBOOT_EXTLINUX_BOOTPREFIXES_${UBOOT_EXTLINUX_TARGETS}[0]}extlinux/exlinux.conf):
+# menu title Select the boot mode
+# TIMEOUT ${UBOOT_EXTLINUX_TIMEOUT}
+# DEFAULT ${UBOOT_EXTLINUX_DEFAULT_LABEL_${UBOOT_EXTLINUX_TARGETS}[1]}
+# LABEL ${UBOOT_EXTLINUX_LABELS_${UBOOT_EXTLINUX_TARGETS}[1]}[0]
+# KERNEL ${UBOOT_EXTLINUX_KERNEL} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_KERNEL_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# FDT ${UBOOT_EXTLINUX_FDT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_FDT_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# APPEND ${UBOOT_EXTLINUX_ROOT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_ROOT_${IMAGE_UBOOT_EXTLINUX_LABELS}[0]} >
+# LABEL ${UBOOT_EXTLINUX_LABELS_${UBOOT_EXTLINUX_TARGETS}[1]}[1]
+# KERNEL ${UBOOT_EXTLINUX_KERNEL} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_KERNEL_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+# FDT ${UBOOT_EXTLINUX_FDT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_FDT_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+# APPEND ${UBOOT_EXTLINUX_ROOT} < OR OVERRIDE WITH : ${UBOOT_EXTLINUX_ROOT_${IMAGE_UBOOT_EXTLINUX_LABELS}[1]} >
+# -----------------------------------------------------------------------------
+
+# Set extlinux console for stm32mp machine
+UBOOT_EXTLINUX_CONSOLE = "console=${@d.getVar('SERIAL_CONSOLE').split()[1]},${@d.getVar('SERIAL_CONSOLE').split()[0]}"
+
+# -----------------------------------------------------------------------------
+# PHYCORE STM32mp1-1 configuration
+# -----------------------------------------------------------------------------
+# Define available targets to use
+UBOOT_EXTLINUX_CONFIGURED_TARGETS += "mp1-1_sdcard"
+UBOOT_EXTLINUX_CONFIGURED_TARGETS += "mp1-1_nor-emmc"
+# Define bootprefix for each target
+UBOOT_EXTLINUX_BOOTPREFIXES_mp1-1_sdcard = "${EXTLINUX_BOOTDEVICE_SDCARD}_phycore-stm32mp1-1_"
+UBOOT_EXTLINUX_BOOTPREFIXES_mp1-1_nor-emmc = "${EXTLINUX_BOOTDEVICE_NOREMMC}_phycore-stm32mp1-1_"
+# Define labels for each target
+UBOOT_EXTLINUX_LABELS_mp1-1_sdcard = "phycore-stm32mp1-sdcard"
+UBOOT_EXTLINUX_LABELS_mp1-1_nor-emmc = "phycore-stm32mp1-nor-emmc"
+# Define default boot config for each target
+UBOOT_EXTLINUX_DEFAULT_LABEL_mp1-1_sdcard ?= "phycore-stm32mp1-sdcard"
+UBOOT_EXTLINUX_DEFAULT_LABEL_mp1-1_nor-emmc ?= "phycore-stm32mp1-nor-emmc"
+# Define FDT overrides for all labels
+UBOOT_EXTLINUX_FDT_phycore-stm32mp1-sdcard = "/phycore-stm32mp1-1.dtb"
+UBOOT_EXTLINUX_FDT_phycore-stm32mp1-nor-emmc = "/phycore-stm32mp1-1.dtb"
+# Define ROOT overrides for all labels
+UBOOT_EXTLINUX_ROOT_phycore-stm32mp1-sdcard = "${EXTLINUX_ROOT_SDCARD}"
+UBOOT_EXTLINUX_ROOT_phycore-stm32mp1-nor-emmc = "${EXTLINUX_ROOT_NOREMMC}"
+# -----------------------------------------------------------------------------
+# Append A7 examples labels for each target
+UBOOT_EXTLINUX_LABELS_mp1-1_sdcard += "phycore-stm32mp1-a7-examples-sdcard"
+UBOOT_EXTLINUX_LABELS_mp1-1_nor-emmc += "phycore-stm32mp1-a7-examples-nor-emmc"
+# Define FDT overrides for A7 labels
+UBOOT_EXTLINUX_FDT_phycore-stm32mp1-a7-examples-sdcard = "/phycore-stm32mp1-1-a7-examples.dtb"
+UBOOT_EXTLINUX_FDT_phycore-stm32mp1-a7-examples-nor-emmc = "/phycore-stm32mp1-1-a7-examples.dtb"
+# Define ROOT overrides for A7 labels
+UBOOT_EXTLINUX_ROOT_phycore-stm32mp1-a7-examples-sdcard = "${EXTLINUX_ROOT_SDCARD}"
+UBOOT_EXTLINUX_ROOT_phycore-stm32mp1-a7-examples-nor-emmc = "${EXTLINUX_ROOT_NOREMMC}"
+# -----------------------------------------------------------------------------
+# Append M4 examples labels for each target
+UBOOT_EXTLINUX_LABELS_mp1-1_sdcard += "phycore-stm32mp1-m4-examples-sdcard"
+UBOOT_EXTLINUX_LABELS_mp1-1_nor-emmc += "phycore-stm32mp1-m4-examples-nor-emmc"
+# Define FDT overrides for M4 labels
+UBOOT_EXTLINUX_FDT_phycore-stm32mp1-m4-examples-sdcard = "/phycore-stm32mp1-1-m4-examples.dtb"
+UBOOT_EXTLINUX_FDT_phycore-stm32mp1-m4-examples-nor-emmc = "/phycore-stm32mp1-1-m4-examples.dtb"
+# Define ROOT overrides for M4 labels
+UBOOT_EXTLINUX_ROOT_phycore-stm32mp1-m4-examples-sdcard = "${EXTLINUX_ROOT_SDCARD}"
+UBOOT_EXTLINUX_ROOT_phycore-stm32mp1-m4-examples-nor-emmc = "${EXTLINUX_ROOT_NOREMMC}"
+
diff --git a/conf/machine/include/phytec-machine-features-stm32mp.inc b/conf/machine/include/phytec-machine-features-stm32mp.inc
new file mode 100644
index 0000000..8fc2f81
--- /dev/null
+++ b/conf/machine/include/phytec-machine-features-stm32mp.inc
@@ -0,0 +1,54 @@
+#@DESCRIPTION: Machine features definitions for STM32 systems
+
+include conf/machine/include/gpu_vivante.inc
+
+#------------------
+#
+# GPU
+#
+# To support gpu on a machine,
+# please add "gpu" to MACHINE_FEATURES in machine conf file
+
+GPU_LIST = "kernel-module-galcore"
+GPU_IMAGE_INSTALL = "${@bb.utils.contains('MACHINE_FEATURES', 'gpu', '${GPU_LIST}', '', d)} "
+
+#------------------
+#
+# optee
+#
+
+OPTEE_LIST = "optee-os-stm32mp"
+OPTEE_IMAGE_INSTALL = "${@bb.utils.contains('COMBINED_FEATURES', 'optee', '${OPTEE_LIST}', '', d)} "
+PREFERRED_PROVIDER_optee-os = "optee-os-stm32mp"
+
+OPTEE_BINARY = "optee-os-stm32mp"
+OPTEE_BINARY_INSTALL = "${@bb.utils.contains('MACHINE_FEATURES', 'optee', '${OPTEE_BINARY}', '', d)} "
+
+#------------------
+#
+# Alsa
+#
+ALSA_ADDONS = "alsa-state-stm32mp1"
+ALSA_ADDONS_INSTALL = "${@bb.utils.contains('COMBINED_FEATURES', 'alsa', '${ALSA_ADDONS}', '', d)} "
+
+#------------------
+#
+# bluetooth
+#
+BLUETOOTH_LIST = " linux-firmware-bluetooth-bcm4343 "
+BLUETOOTH_IMAGE_INSTALL = "${@bb.utils.contains('MACHINE_FEATURES', 'bluetooth', '${BLUETOOTH_LIST}', '', d)} "
+
+#------------------
+#
+# Image appends
+#
+EXTRA_IMAGEDEPENDS_append = " \
+ ${OPTEE_BINARY_INSTALL} \
+ "
+
+MACHINE_EXTRA_RRECOMMENDS_append = " \
+ ${GPU_IMAGE_INSTALL} \
+ ${OPTEE_IMAGE_INSTALL} \
+ ${ALSA_ADDONS_INSTALL} \
+ ${BLUETOOTH_IMAGE_INSTALL}\
+ "
diff --git a/conf/machine/include/phytec-machine-flashlayout-deleteall-stm32mp.inc b/conf/machine/include/phytec-machine-flashlayout-deleteall-stm32mp.inc
new file mode 100644
index 0000000..7d06d99
--- /dev/null
+++ b/conf/machine/include/phytec-machine-flashlayout-deleteall-stm32mp.inc
@@ -0,0 +1,65 @@
+#@DESCRIPTION: STM32MP machine flashlayout deleteall configuration
+
+# Set configuration file to monitor
+FLASHLAYOUT_CONFIGURE_FILES_append = " ${PHYCORE_STM32MP_BASE}/conf/machine/include/phytec-machine-flashlayout-deleteall-stm32mp.inc:True "
+
+# -----------------------------------------------------------------------------
+# Define config labels
+# -----------------------------------------------------------------------------
+FLASHLAYOUT_CONFIG_LABELS_deleteall = "phycore"
+
+# -----------------------------------------------------------------------------
+# Define label types
+# -----------------------------------------------------------------------------
+FLASHLAYOUT_TYPE_LABELS_deleteall_phycore = "${STM32MP_DT_FILES_PHYCORE}"
+
+# -----------------------------------------------------------------------------
+# Define partitions to use
+#
+# NB: To manage bootloader partitions, simplification is done by directly
+# re-using 'fsbl1-boot' and 'ssbl-boot' partitions already defined in file
+# 'phytec-machine-flashlayout-stm32mp.inc'
+# -----------------------------------------------------------------------------
+FLASHLAYOUT_PARTITION_LABELS_deleteall_phycore = "fsbl1-boot ssbl-boot sdcard-all"
+
+# -----------------------------------------------------------------------------
+# Partition configuration for each partition label
+FLASHLAYOUT_PARTITION_ENABLE_emmc-fsbl1 = "PED"
+FLASHLAYOUT_PARTITION_ENABLE_emmc-fsbl2 = "PED"
+FLASHLAYOUT_PARTITION_ENABLE_emmc-all = "PED"
+FLASHLAYOUT_PARTITION_ENABLE_nand-4-256-all = "PED"
+FLASHLAYOUT_PARTITION_ENABLE_nor-all = "PED"
+FLASHLAYOUT_PARTITION_ENABLE_sdcard-all = "PED"
+
+FLASHLAYOUT_PARTITION_ID_emmc-fsbl1 = "0x04"
+FLASHLAYOUT_PARTITION_ID_emmc-fsbl2 = "0x05"
+FLASHLAYOUT_PARTITION_ID_emmc-all = "0x30"
+FLASHLAYOUT_PARTITION_ID_nand-4-256-all = "0x40"
+FLASHLAYOUT_PARTITION_ID_nor-all = "0x50"
+FLASHLAYOUT_PARTITION_ID_sdcard-all = "0x60"
+
+FLASHLAYOUT_PARTITION_TYPE_emmc-all = "RawImage"
+FLASHLAYOUT_PARTITION_TYPE_nand-4-256-all = "RawImage"
+FLASHLAYOUT_PARTITION_TYPE_nor-all = "RawImage"
+FLASHLAYOUT_PARTITION_TYPE_sdcard-all = "RawImage"
+
+FLASHLAYOUT_PARTITION_DEVICE_emmc-fsbl1 = "${DEVICE_EMMC}"
+FLASHLAYOUT_PARTITION_DEVICE_emmc-fsbl2 = "${DEVICE_EMMC}"
+FLASHLAYOUT_PARTITION_DEVICE_emmc-all = "${DEVICE_EMMC}"
+FLASHLAYOUT_PARTITION_DEVICE_nand-4-256-all = "${DEVICE_NAND}"
+FLASHLAYOUT_PARTITION_DEVICE_nor-all = "${DEVICE_NOR}"
+FLASHLAYOUT_PARTITION_DEVICE_sdcard-all = "${DEVICE_SDCARD}"
+# Specific for fsbl1-boot ssbl-boot partitions
+FLASHLAYOUT_PARTITION_DEVICE_deleteall_fsbl1-boot = "none"
+FLASHLAYOUT_PARTITION_DEVICE_deleteall_ssbl-boot = "none"
+
+FLASHLAYOUT_PARTITION_OFFSET_deleteall = "0x0"
+FLASHLAYOUT_PARTITION_OFFSET_deleteall_emmc-fsbl1 = "${FLASHLAYOUT_PARTITION_OFFSET_emmc_fsbl1}"
+FLASHLAYOUT_PARTITION_OFFSET_deleteall_emmc-fsbl2 = "${FLASHLAYOUT_PARTITION_OFFSET_emmc_fsbl2}"
+
+# -----------------------------------------------------------------------------
+# The 'deletall' bootscheme is a trick to generate flashlayout files to clean
+# all memory devices on board. There are no specific 'deleteall' bootloader
+# binaries so use the 'trusted' or 'optee' one.
+BIN2BOOT_REPLACE_PATTERNS_fsbl1-boot_append = " deleteall;trusted"
+BIN2BOOT_REPLACE_PATTERNS_ssbl-boot_append = " ${@bb.utils.contains('BOOTSCHEME_LABELS', 'optee', 'deleteall;optee', 'deleteall;trusted', d)}"
diff --git a/conf/machine/include/phytec-machine-flashlayout-stm32mp.inc b/conf/machine/include/phytec-machine-flashlayout-stm32mp.inc
new file mode 100644
index 0000000..8e3e4a8
--- /dev/null
+++ b/conf/machine/include/phytec-machine-flashlayout-stm32mp.inc
@@ -0,0 +1,291 @@
+#@DESCRIPTION: STM32MP machine flashlayout configuration
+
+INHERIT += "flashlayout-stm32mp"
+
+# Set configuration file to monitor
+FLASHLAYOUT_CONFIGURE_FILES_append = " ${PHYCORE_STM32MP_BASE}/conf/machine/include/phytec-machine-flashlayout-stm32mp.inc:True "
+
+# Add specific dependencies to get all binaries generated before flashlayout files
+FLASHLAYOUT_DEPEND_TASKS += "${@bb.utils.contains('EXTRA_IMAGEDEPENDS', 'tf-a-stm32mp', 'tf-a-stm32mp:do_deploy', '', d)}"
+FLASHLAYOUT_DEPEND_TASKS += "${@bb.utils.contains('EXTRA_IMAGEDEPENDS', 'u-boot-stm32mp', 'u-boot-stm32mp:do_deploy', '', d)}"
+FLASHLAYOUT_DEPEND_TASKS += "${@bb.utils.contains('EXTRA_IMAGEDEPENDS', 'optee-os-stm32mp', 'optee-os-stm32mp:do_deploy', '', d)}"
+
+# -----------------------------------------------------------------------------
+# Define flashlayout devices
+# -----------------------------------------------------------------------------
+DEVICE_EMMC = "mmc1"
+DEVICE_NAND = "nand0"
+DEVICE_NOR = "nor0"
+DEVICE_SDCARD = "mmc0"
+# -----------------------------------------------------------------------------
+# EMMC
+# Extra space is required to store 'Protective MBR' and 'Primary GPT Header'
+# Currently the required size is 17kBytes (i.e. 0x4400)
+# We need to align this size to get the first offset to use
+DEVICE_START_OFFSET_mmc1 = "0x00080000"
+DEVICE_ALIGNMENT_SIZE_mmc1 = "0x00080000"
+# -----------------------------------------------------------------------------
+# NAND
+DEVICE_START_OFFSET_nand0 = "0x00000000"
+DEVICE_ALIGNMENT_SIZE_nand0 = "0x00040000"
+# -----------------------------------------------------------------------------
+# NOR
+DEVICE_START_OFFSET_nor0 = "0x00000000"
+DEVICE_ALIGNMENT_SIZE_nor0 = "0x00010000"
+# -----------------------------------------------------------------------------
+# SDCARD
+# Extra space is required to store 'Protective MBR' and 'Primary GPT Header'
+# Currently the required size is 17kBytes (i.e. 0x4400)
+# We need to align this size to get the first offset to use
+DEVICE_START_OFFSET_mmc0 = "0x00004400"
+DEVICE_ALIGNMENT_SIZE_mmc0 = "0x00000200"
+
+# -----------------------------------------------------------------------------
+# Define bootscheme labels
+# -----------------------------------------------------------------------------
+FLASHLAYOUT_BOOTSCHEME_LABELS ??= "basic optee trusted"
+
+# -----------------------------------------------------------------------------
+# Define config labels
+# -----------------------------------------------------------------------------
+# NOTE: define can be done with following priority assignment:
+# 1) list_<BOOTSCHEME>
+# 2) list
+# 3) Default 'list' to 'none' when not defined
+# -----------------------------------------------------------------------------
+FLASHLAYOUT_CONFIG_LABELS ??= "emmc nand-4-256 nor-sdcard nor-emmc nor-nand-4-256 sdcard"
+
+# -----------------------------------------------------------------------------
+# Define label types
+# -----------------------------------------------------------------------------
+# NOTE: define can be done with following priority assignment:
+# 1) list_<BOOTSCHEME>_<CONFIG>
+# 2) list_<BOOTSCHEME>
+# 3) list_<CONFIG>
+# 4) list
+# 5) Default 'list' to 'none' when not defined
+# -----------------------------------------------------------------------------
+# EMMC
+# Set flashlayout file generation to eval board (mother and daughter) only
+FLASHLAYOUT_TYPE_LABELS_emmc = "${STM32MP_DT_FILES_PHYCORE}"
+# NAND
+# Set flashlayout file generation to eval board only
+FLASHLAYOUT_TYPE_LABELS_nand-4-256 = "${STM32MP_DT_FILES_PHYCORE}"
+# NOR
+# Set flashlayout file generation to eval board only
+FLASHLAYOUT_TYPE_LABELS_nor-emmc = "${STM32MP_DT_FILES_PHYCORE}"
+FLASHLAYOUT_TYPE_LABELS_nor-nand-4-256 = "${STM32MP_DT_FILES_PHYCORE}"
+FLASHLAYOUT_TYPE_LABELS_nor-sdcard = "${STM32MP_DT_FILES_PHYCORE}"
+# SDCARD
+# Set flashlayout file generation for all boards
+FLASHLAYOUT_TYPE_LABELS_sdcard = "${STM32MP_DT_FILES_PHYCORE}"
+
+# -----------------------------------------------------------------------------
+# Define partitions to use
+# -----------------------------------------------------------------------------
+# There are few restrictions to follow:
+# - The partition for the first boot loader should follow the naming rule:
+# fsbl*
+# - The partition for the secondary boot loader should follow the naming rule:
+# ssbl
+# -----------------------------------------------------------------------------
+# NOTE: define can be done with following priority assignment:
+# 1) list_<BOOTSCHEME>_<CONFIG>
+# 2) list_<BOOTSCHEME>
+# 3) list_<CONFIG>
+# 4) list
+# 5) Default 'list' to 'none' when not defined
+# -----------------------------------------------------------------------------
+FLASHLAYOUT_PARTITION_LABELS_basic_emmc = "fsbl1-boot ssbl-boot fsbl1 fsbl2 ssbl"
+FLASHLAYOUT_PARTITION_LABELS_basic_nand-4-256 = "none"
+FLASHLAYOUT_PARTITION_LABELS_basic_nor-nand-4-256 = "fsbl1-boot ssbl-boot fsbl1 fsbl2 ssbl logo empty"
+FLASHLAYOUT_PARTITION_LABELS_basic_nor-emmc = "fsbl1-boot ssbl-boot fsbl1 fsbl2 ssbl logo empty"
+FLASHLAYOUT_PARTITION_LABELS_basic_nor-sdcard = "fsbl1-boot ssbl-boot fsbl1 fsbl2 ssbl logo empty bootfs vendorfs rootfs userfs"
+FLASHLAYOUT_PARTITION_LABELS_basic_sdcard = "fsbl1-boot ssbl-boot fsbl1 fsbl2 ssbl bootfs vendorfs rootfs userfs"
+
+FLASHLAYOUT_PARTITION_LABELS_optee_emmc = "fsbl1-boot ssbl-boot fsbl1 fsbl2 ssbl teeh teed teex bootfs vendorfs rootfs userfs"
+FLASHLAYOUT_PARTITION_LABELS_optee_nand-4-256 = "fsbl1-boot ssbl-boot fsbl1 ssbl ssbl2 teeh teed teex ubifs"
+FLASHLAYOUT_PARTITION_LABELS_optee_nor-nand-4-256 = "fsbl1-boot ssbl-boot fsbl1 fsbl2 ssbl logo teeh teed teex empty empty2 empty3 ubifs"
+FLASHLAYOUT_PARTITION_LABELS_optee_nor-emmc = "fsbl1-boot ssbl-boot fsbl1 fsbl2 ssbl logo teeh teed teex empty bootfs vendorfs rootfs userfs"
+FLASHLAYOUT_PARTITION_LABELS_optee_nor-sdcard = "fsbl1-boot ssbl-boot fsbl1 fsbl2 ssbl logo teeh teed teex empty bootfs vendorfs rootfs userfs"
+FLASHLAYOUT_PARTITION_LABELS_optee_sdcard = "fsbl1-boot ssbl-boot fsbl1 fsbl2 ssbl teeh teed teex bootfs vendorfs rootfs userfs"
+
+FLASHLAYOUT_PARTITION_LABELS_trusted_emmc = "fsbl1-boot ssbl-boot fsbl1 fsbl2 ssbl bootfs vendorfs rootfs userfs"
+FLASHLAYOUT_PARTITION_LABELS_trusted_nand-4-256 = "fsbl1-boot ssbl-boot fsbl1 ssbl ssbl2 ubifs"
+FLASHLAYOUT_PARTITION_LABELS_trusted_nor-nand-4-256 = "fsbl1-boot ssbl-boot fsbl1 fsbl2 ssbl logo empty empty2 empty3 ubifs"
+FLASHLAYOUT_PARTITION_LABELS_trusted_nor-emmc = "fsbl1-boot ssbl-boot fsbl1 fsbl2 ssbl logo empty bootfs vendorfs rootfs userfs"
+FLASHLAYOUT_PARTITION_LABELS_trusted_nor-sdcard = "fsbl1-boot ssbl-boot fsbl1 fsbl2 ssbl logo empty bootfs vendorfs rootfs userfs"
+FLASHLAYOUT_PARTITION_LABELS_trusted_sdcard = "fsbl1-boot ssbl-boot fsbl1 fsbl2 ssbl bootfs vendorfs rootfs userfs"
+
+# -----------------------------------------------------------------------------
+# Partition configuration for each partition label
+# NOTE: each item can be defined with following priority assignment:
+# 1) item_<BOOTSCHEME>_<CONFIG>_<PARTITION>
+# 2) item_<BOOTSCHEME>_<CONFIG>
+# 3) item_<BOOTSCHEME>_<PARTITION>
+# 4) item_<BOOTSCHEME>
+# 5) item_<CONFIG>_<PARTITION>
+# 6) item_<CONFIG>
+# 7) item_<PARTITION>
+# 8) item
+# 9) Default 'item' to 'none' when not defined
+# -----------------------------------------------------------------------------
+FLASHLAYOUT_PARTITION_ENABLE = "P"
+FLASHLAYOUT_PARTITION_ENABLE_fsbl1-boot = "-"
+FLASHLAYOUT_PARTITION_ENABLE_ssbl-boot = "-"
+FLASHLAYOUT_PARTITION_ENABLE_empty = "PE"
+FLASHLAYOUT_PARTITION_ENABLE_empty2 = "PE"
+FLASHLAYOUT_PARTITION_ENABLE_empty3 = "PE"
+FLASHLAYOUT_PARTITION_ENABLE_logo = "PE"
+
+# -----------------------------------------------------------------------------
+# Partition ID
+# -----------------------------------------------------------------------------
+# The STM32CubeProgrammer supported ID range is:
+# 0x00 to 0xFF
+# Some IDs are reserved for internal usage on STM32CubeProgrammer and special
+# management is implemented for binary with STM32 header. This means that for
+# flashlayout files, available ID range is only:
+# 0x01 to 0x0F for Boot partitions with STM32 header
+# 0x10 to 0xF0 for User partitions programmed without header
+# Note also that for FSBL and SSBL binaries loaded in RAM to program the devices
+# there are two reserved IDs
+# 0x01 for FSBL
+# 0x03 for SSBL
+FLASHLAYOUT_PARTITION_ID_fsbl1-boot = "0x01"
+FLASHLAYOUT_PARTITION_ID_ssbl-boot = "0x03"
+FLASHLAYOUT_PARTITION_ID_fsbl1 = "0x04"
+FLASHLAYOUT_PARTITION_ID_fsbl2 = "0x05"
+FLASHLAYOUT_PARTITION_ID_ssbl = "0x06"
+FLASHLAYOUT_PARTITION_ID_ssbl2 = "0x07"
+FLASHLAYOUT_PARTITION_ID_teeh = "0x0A"
+FLASHLAYOUT_PARTITION_ID_teed = "0x0B"
+FLASHLAYOUT_PARTITION_ID_teex = "0x0C"
+FLASHLAYOUT_PARTITION_ID_empty = "0x10"
+FLASHLAYOUT_PARTITION_ID_empty2 = "0x11"
+FLASHLAYOUT_PARTITION_ID_empty3 = "0x12"
+FLASHLAYOUT_PARTITION_ID_logo = "0x20"
+FLASHLAYOUT_PARTITION_ID_ubifs = "0x21"
+FLASHLAYOUT_PARTITION_ID_bootfs = "0x21"
+FLASHLAYOUT_PARTITION_ID_vendorfs = "0x22"
+FLASHLAYOUT_PARTITION_ID_rootfs = "0x23"
+FLASHLAYOUT_PARTITION_ID_userfs = "0x24"
+
+FLASHLAYOUT_PARTITION_TYPE = "Binary"
+FLASHLAYOUT_PARTITION_TYPE_nand-4-256_fsbl1 = "Binary(2)"
+FLASHLAYOUT_PARTITION_TYPE_ubifs = "System"
+FLASHLAYOUT_PARTITION_TYPE_bootfs = "System"
+FLASHLAYOUT_PARTITION_TYPE_vendorfs = "FileSystem"
+FLASHLAYOUT_PARTITION_TYPE_rootfs = "FileSystem"
+FLASHLAYOUT_PARTITION_TYPE_userfs = "FileSystem"
+
+FLASHLAYOUT_PARTITION_DEVICE_emmc = "${DEVICE_EMMC}"
+FLASHLAYOUT_PARTITION_DEVICE_nand-4-256 = "${DEVICE_NAND}"
+FLASHLAYOUT_PARTITION_DEVICE_nor = "${DEVICE_NOR}"
+FLASHLAYOUT_PARTITION_DEVICE_nor-emmc = "${DEVICE_NOR}"
+FLASHLAYOUT_PARTITION_DEVICE_nor-emmc_bootfs = "${DEVICE_EMMC}"
+FLASHLAYOUT_PARTITION_DEVICE_nor-emmc_vendorfs = "${DEVICE_EMMC}"
+FLASHLAYOUT_PARTITION_DEVICE_nor-emmc_rootfs = "${DEVICE_EMMC}"
+FLASHLAYOUT_PARTITION_DEVICE_nor-emmc_userfs = "${DEVICE_EMMC}"
+FLASHLAYOUT_PARTITION_DEVICE_nor-nand-4-256 = "${DEVICE_NOR}"
+FLASHLAYOUT_PARTITION_DEVICE_nor-nand-4-256_empty2 = "${DEVICE_NAND}"
+FLASHLAYOUT_PARTITION_DEVICE_nor-nand-4-256_empty3 = "${DEVICE_NAND}"
+FLASHLAYOUT_PARTITION_DEVICE_nor-nand-4-256_ubifs = "${DEVICE_NAND}"
+FLASHLAYOUT_PARTITION_DEVICE_nor-sdcard = "${DEVICE_NOR}"
+FLASHLAYOUT_PARTITION_DEVICE_nor-sdcard_bootfs = "${DEVICE_SDCARD}"
+FLASHLAYOUT_PARTITION_DEVICE_nor-sdcard_vendorfs = "${DEVICE_SDCARD}"
+FLASHLAYOUT_PARTITION_DEVICE_nor-sdcard_rootfs = "${DEVICE_SDCARD}"
+FLASHLAYOUT_PARTITION_DEVICE_nor-sdcard_userfs = "${DEVICE_SDCARD}"
+FLASHLAYOUT_PARTITION_DEVICE_sdcard = "${DEVICE_SDCARD}"
+# Specific for fsbl1-boot ssbl-boot partitions
+FLASHLAYOUT_PARTITION_DEVICE_basic_fsbl1-boot = "none"
+FLASHLAYOUT_PARTITION_DEVICE_basic_ssbl-boot = "none"
+FLASHLAYOUT_PARTITION_DEVICE_optee_fsbl1-boot = "none"
+FLASHLAYOUT_PARTITION_DEVICE_optee_ssbl-boot = "none"
+FLASHLAYOUT_PARTITION_DEVICE_trusted_fsbl1-boot = "none"
+FLASHLAYOUT_PARTITION_DEVICE_trusted_ssbl-boot = "none"
+
+FLASHLAYOUT_PARTITION_OFFSET_fsbl1-boot = "0x0"
+FLASHLAYOUT_PARTITION_OFFSET_ssbl-boot = "0x0"
+FLASHLAYOUT_PARTITION_OFFSET_emmc_fsbl1 = "boot1"
+FLASHLAYOUT_PARTITION_OFFSET_emmc_fsbl2 = "boot2"
+FLASHLAYOUT_PARTITION_OFFSET_emmc_ssbl = "${DEVICE_START_OFFSET_mmc1}"
+FLASHLAYOUT_PARTITION_OFFSET_nand-4-256_fsbl1 = "${DEVICE_START_OFFSET_nand0}"
+FLASHLAYOUT_PARTITION_OFFSET_nor-sdcard_fsbl1 = "${DEVICE_START_OFFSET_nor0}"
+FLASHLAYOUT_PARTITION_OFFSET_nor-sdcard_bootfs = "${DEVICE_START_OFFSET_mmc0}"
+FLASHLAYOUT_PARTITION_OFFSET_nor-emmc_fsbl1 = "${DEVICE_START_OFFSET_nor0}"
+FLASHLAYOUT_PARTITION_OFFSET_nor-emmc_bootfs = "${DEVICE_START_OFFSET_mmc1}"
+FLASHLAYOUT_PARTITION_OFFSET_nor-nand-4-256_fsbl1 = "${DEVICE_START_OFFSET_nor0}"
+FLASHLAYOUT_PARTITION_OFFSET_nor-nand-4-256_empty2 = "${DEVICE_START_OFFSET_nand0}"
+FLASHLAYOUT_PARTITION_OFFSET_sdcard_fsbl1 = "${DEVICE_START_OFFSET_mmc0}"
+
+# Size defined in Kbytes
+FLASHLAYOUT_PARTITION_SIZE_fsbl1 = "256"
+FLASHLAYOUT_PARTITION_SIZE_nand-4-256_fsbl1 = "2048"
+FLASHLAYOUT_PARTITION_SIZE_fsbl2 = "256"
+FLASHLAYOUT_PARTITION_SIZE_ssbl = "2048"
+FLASHLAYOUT_PARTITION_SIZE_ssbl2 = "2048"
+FLASHLAYOUT_PARTITION_SIZE_logo = "256"
+FLASHLAYOUT_PARTITION_SIZE_teeh = "256"
+FLASHLAYOUT_PARTITION_SIZE_teed = "256"
+FLASHLAYOUT_PARTITION_SIZE_teex = "256"
+FLASHLAYOUT_PARTITION_SIZE_empty = "0"
+FLASHLAYOUT_PARTITION_SIZE_empty2 = "${FLASHLAYOUT_PARTITION_SIZE_nand-4-256_fsbl1}"
+FLASHLAYOUT_PARTITION_SIZE_empty3 = "${FLASHLAYOUT_PARTITION_SIZE_ssbl}"
+# Specific override for partition size as the configuration should follow
+# the U-Boot source code where these partition sizes are hard coded
+FLASHLAYOUT_PARTITION_SIZE_nand-4-256_teeh = "512"
+FLASHLAYOUT_PARTITION_SIZE_nand-4-256_teed = "512"
+FLASHLAYOUT_PARTITION_SIZE_nand-4-256_teex = "512"
+
+FLASHLAYOUT_PARTITION_SIZE_bootfs = "${BOOTFS_PARTITION_SIZE}"
+FLASHLAYOUT_PARTITION_SIZE_vendorfs = "${VENDORFS_PARTITION_SIZE}"
+FLASHLAYOUT_PARTITION_SIZE_rootfs = "${ROOTFS_PARTITION_SIZE}"
+FLASHLAYOUT_PARTITION_SIZE_ubifs = "none"
+FLASHLAYOUT_PARTITION_SIZE_userfs = "${USERFS_PARTITION_SIZE}"
+
+# Set binaries to use for each partition
+FLASHLAYOUT_PARTITION_BIN2LOAD_fsbl1-boot = "tf-a.stm32"
+FLASHLAYOUT_PARTITION_BIN2LOAD_ssbl-boot = "u-boot.stm32"
+FLASHLAYOUT_PARTITION_BIN2LOAD_fsbl1 = "tf-a.stm32"
+FLASHLAYOUT_PARTITION_BIN2LOAD_basic_fsbl1 = "u-boot-spl.stm32"
+FLASHLAYOUT_PARTITION_BIN2LOAD_fsbl2 = "tf-a.stm32"
+FLASHLAYOUT_PARTITION_BIN2LOAD_basic_fsbl2 = "u-boot-spl.stm32"
+FLASHLAYOUT_PARTITION_BIN2LOAD_ssbl = "u-boot.stm32"
+FLASHLAYOUT_PARTITION_BIN2LOAD_basic_ssbl = "u-boot.img"
+FLASHLAYOUT_PARTITION_BIN2LOAD_ssbl2 = "u-boot.stm32"
+FLASHLAYOUT_PARTITION_BIN2LOAD_teeh = "tee-header_v2.stm32"
+FLASHLAYOUT_PARTITION_BIN2LOAD_teed = "tee-pageable_v2.stm32"
+FLASHLAYOUT_PARTITION_BIN2LOAD_teex = "tee-pager_v2.stm32"
+FLASHLAYOUT_PARTITION_BIN2LOAD_logo = "none"
+FLASHLAYOUT_PARTITION_BIN2LOAD_ubifs = "${IMAGE_LINK_NAME}_nand_4_256_multivolume.ubi"
+FLASHLAYOUT_PARTITION_BIN2LOAD_bootfs = "${STM32MP_BOOTFS_IMAGE}-${DISTRO}-${MACHINE}.ext4"
+FLASHLAYOUT_PARTITION_BIN2LOAD_vendorfs = "${STM32MP_VENDORFS_IMAGE}-${DISTRO}-${MACHINE}.ext4"
+FLASHLAYOUT_PARTITION_BIN2LOAD_rootfs = "${IMAGE_LINK_NAME}.ext4"
+FLASHLAYOUT_PARTITION_BIN2LOAD_userfs = "${STM32MP_USERFS_IMAGE}-${DISTRO}-${MACHINE}.ext4"
+
+# -----------------------------------------------------------------------------
+# Use the 'BIN2BOOT_REPLACE_PATTERNS' var to allow dynamic binary renaming for
+# the bootloader binaries. This is only required for fsbl1-boot and ssbl-boot
+# partitions that provides the binary to flash the device.
+# The format to follow is:
+# '<PATTERN2REPLACE_1>;<PATTERN2SET_1> <PATTERN2REPLACE_2>;<PATTERN2SET_2>'
+# And the pattern to replace in binary name is only searched as:
+# '-<PATTERN>$'
+# or
+# '-<PATTERN>-'
+# -----------------------------------------------------------------------------
+# The 'basic' bootscheme does not support Programmer mode, so use 'trusted' one
+# (valid for both fsbl1-boot and ssbl-boot)
+BIN2BOOT_REPLACE_PATTERNS_DEFAULT = "basic;trusted"
+# The daughter board does not support Programmer mode, so use eval one
+# (valid for both fsbl1-boot and ssbl-boot)
+BIN2BOOT_REPLACE_PATTERNS_DEFAULT_append = " ed1;ev1"
+
+# Apply for fsbl1-boot and ssbl-boot
+BIN2BOOT_REPLACE_PATTERNS_fsbl1-boot = "${BIN2BOOT_REPLACE_PATTERNS_DEFAULT}"
+BIN2BOOT_REPLACE_PATTERNS_ssbl-boot = "${BIN2BOOT_REPLACE_PATTERNS_DEFAULT}"
+
+# For fsbl1-boot, the 'optee' bootscheme does not support Programmer mode, so
+# prefer the 'trusted' one.
+BIN2BOOT_REPLACE_PATTERNS_fsbl1-boot_append = " optee;trusted"
diff --git a/conf/machine/phycore-stm32mp1-1.conf b/conf/machine/phycore-stm32mp1-1.conf
new file mode 100644
index 0000000..37908a5
--- /dev/null
+++ b/conf/machine/phycore-stm32mp1-1.conf
@@ -0,0 +1,93 @@
+
+#@TYPE: Machine
+#@NAME: phycore-stm32mp1-1
+#@DESCRIPTION: Configuration for phyCORE-STM32MP1-1 Dev Board - PCM-068-1534-0-00/PCM-939-1517-1-002 (Trusted boot and SDcard only)
+#@NEEDED_BSPLAYERS:
+
+include conf/machine/include/phytec-machine-common-stm32mp.inc
+
+MACHINEOVERRIDES .= ":phycore"
+
+EULA_FILE_ST_stm32mpcommon = "${PHYCORE_STM32MP_BASE}/conf/eula/${MACHINE}"
+EULA_FILE_ST_MD5SUM_stm32mpcommon = "8b505090fb679839cefbcc784afe8ce9"
+
+# =========================================================================
+# Chip architecture
+# =========================================================================
+DEFAULTTUNE = "cortexa7thf-neon-vfpv4"
+include conf/machine/include/tune-cortexa7.inc
+
+# =========================================================================
+# boot scheme
+# =========================================================================
+#BOOTSCHEME_LABELS += "basic"
+BOOTSCHEME_LABELS += "trusted"
+#BOOTSCHEME_LABELS += "optee"
+
+
+PREFERRED_VERSION_u-boot-stm32mp = "2018.11"
+
+# =========================================================================
+# Machine settings
+# =========================================================================
+STM32MP_DT_FILES_PHYCORE += "phycore-stm32mp1-1"
+
+# =========================================================================
+# Machine features
+# =========================================================================
+MACHINE_FEATURES += "bluetooth"
+MACHINE_FEATURES += "wifi"
+MACHINE_FEATURES += "${@'gpu' if d.getVar('ACCEPT_EULA_'+d.getVar('MACHINE')) == '1' else ''}"
+# Splashscreen enabled
+MACHINE_FEATURES += "splashscreen"
+
+# =========================================================================
+# Image
+# =========================================================================
+# Add ubi FSTYPES to default ones for nand volumes
+#IMAGE_FSTYPES += "stmultiubi"
+
+# =========================================================================
+# Kernel
+# =========================================================================
+# Kernel config
+# Set this address to 0xC2000040, which is 0xC2000000 + 0x40.
+# 0xC2000000 is the memory address where U-Boot will copy from flash the file uImage and 0x40 is uImage header size (64Bytes).
+# With this value, U-Boot will be able to execute in place the zImage contained in uImage.
+ST_KERNEL_LOADADDR = "0xC2000040"
+
+# For eval board: auto-load goodix module (touchscreen module)
+#KERNEL_MODULE_AUTOLOAD = "goodix"
+
+# Define the devicetree for Linux A7 examples
+LINUX_A7_EXAMPLES_DT += "phycore-stm32mp1-1-a7-examples"
+
+
+PREFERRED_VERSION_linux-stm32mp = "4.19"
+
+# =========================================================================
+# flashlayout
+# =========================================================================
+# Define the config labels to use to generate flashlayout file
+#FLASHLAYOUT_CONFIG_LABELS += "emmc"
+#FLASHLAYOUT_CONFIG_LABELS += "nand-4-256"
+#FLASHLAYOUT_CONFIG_LABELS += "nor-sdcard"
+FLASHLAYOUT_CONFIG_LABELS += "nor-emmc"
+#FLASHLAYOUT_CONFIG_LABELS += "nor-nand-4-256"
+FLASHLAYOUT_CONFIG_LABELS += "sdcard"
+
+# =========================================================================
+# M4 copro
+# =========================================================================
+# Define the devicetree for M4 example
+CUBE_M4_EXAMPLES_DT += "phycore-stm32mp1-1-m4-examples"
+
+# Define specific board reference to use
+M4_BOARDS = "STM32MP157C-PHY"
+
+# =========================================================================
+# extlinux configuration
+# =========================================================================
+# As example, modify the default boot config for each target to M4 config
+UBOOT_EXTLINUX_DEFAULT_LABEL_mp1-1_sdcard = "phycore-stm32mp1-examples-sdcard"
+UBOOT_EXTLINUX_DEFAULT_LABEL_mp1-1_sdcard-optee = "phycore-stm32mp1-m4-examples-sdcard-optee"
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-bsp/alsa/alsa-state-stm32mp1.bbappend b/dynamic-layers/stm-st-stm32mp/recipes-bsp/alsa/alsa-state-stm32mp1.bbappend
new file mode 100644
index 0000000..d93cf5b
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-bsp/alsa/alsa-state-stm32mp1.bbappend
@@ -0,0 +1,7 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+# Machine specific
+
+SRC_URI += " \
+ file://asound-phycore-stm32mp1-1.state \
+ file://asound-phycore-stm32mp1-1.conf \
+ "
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-bsp/alsa/alsa-state-stm32mp1/asound-phycore-stm32mp1-1.conf b/dynamic-layers/stm-st-stm32mp/recipes-bsp/alsa/alsa-state-stm32mp1/asound-phycore-stm32mp1-1.conf
new file mode 100644
index 0000000..aa466e8
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-bsp/alsa/alsa-state-stm32mp1/asound-phycore-stm32mp1-1.conf
@@ -0,0 +1,12 @@
+pcm.!playback_codec {
+ type hw
+ card STM32MP1PHYCORE
+ device 0
+}
+
+pcm.!record_codec {
+ type hw
+ card STM32MP1PHYCORE
+ device 1
+}
+
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-bsp/alsa/alsa-state-stm32mp1/asound-phycore-stm32mp1-1.state b/dynamic-layers/stm-st-stm32mp/recipes-bsp/alsa/alsa-state-stm32mp1/asound-phycore-stm32mp1-1.state
new file mode 100644
index 0000000..0bc0f28
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-bsp/alsa/alsa-state-stm32mp1/asound-phycore-stm32mp1-1.state
@@ -0,0 +1,1205 @@
+state.STM32MP1PHYCORE {
+ control.1 {
+ iface MIXER
+ name 'Class-D Playback Volume'
+ value.0 0
+ value.1 0
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 3'
+ dbmin 0
+ dbmax 1800
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.2 {
+ iface MIXER
+ name 'PCM Playback Volume'
+ value.0 127
+ value.1 127
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 127'
+ dbmin -6350
+ dbmax 0
+ dbvalue.0 0
+ dbvalue.1 0
+ }
+ }
+ control.3 {
+ iface MIXER
+ name 'Left Line Mixer Line2R Bypass Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.4 {
+ iface MIXER
+ name 'Left Line Mixer PGAR Bypass Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.5 {
+ iface MIXER
+ name 'Left Line Mixer DACR1 Playback Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.6 {
+ iface MIXER
+ name 'Right Line Mixer Line2L Bypass Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.7 {
+ iface MIXER
+ name 'Right Line Mixer PGAL Bypass Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.8 {
+ iface MIXER
+ name 'Right Line Mixer DACL1 Playback Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.9 {
+ iface MIXER
+ name 'Left HP Mixer Line2R Bypass Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.10 {
+ iface MIXER
+ name 'Left HP Mixer PGAR Bypass Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.11 {
+ iface MIXER
+ name 'Left HP Mixer DACR1 Playback Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.12 {
+ iface MIXER
+ name 'Right HP Mixer Line2L Bypass Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.13 {
+ iface MIXER
+ name 'Right HP Mixer PGAL Bypass Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.14 {
+ iface MIXER
+ name 'Right HP Mixer DACL1 Playback Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.15 {
+ iface MIXER
+ name 'Left HPCOM Mixer Line2R Bypass Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.16 {
+ iface MIXER
+ name 'Left HPCOM Mixer PGAR Bypass Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.17 {
+ iface MIXER
+ name 'Left HPCOM Mixer DACR1 Playback Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.18 {
+ iface MIXER
+ name 'Right HPCOM Mixer Line2L Bypass Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.19 {
+ iface MIXER
+ name 'Right HPCOM Mixer PGAL Bypass Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.20 {
+ iface MIXER
+ name 'Right HPCOM Mixer DACL1 Playback Volume'
+ value 118
+ comment {
+ access 'read write'
+ type INTEGER
+ count 1
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 0
+ }
+ }
+ control.21 {
+ iface MIXER
+ name 'Line Line2 Bypass Volume'
+ value.0 72
+ value.1 72
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 -2300
+ dbvalue.1 -2300
+ }
+ }
+ control.22 {
+ iface MIXER
+ name 'Line PGA Bypass Volume'
+ value.0 85
+ value.1 85
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 -1650
+ dbvalue.1 -1650
+ }
+ }
+ control.23 {
+ iface MIXER
+ name 'Line DAC Playback Volume'
+ value.0 82
+ value.1 82
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 -1800
+ dbvalue.1 -1800
+ }
+ }
+ control.24 {
+ iface MIXER
+ name 'HP Line2 Bypass Volume'
+ value.0 71
+ value.1 71
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 -2350
+ dbvalue.1 -2350
+ }
+ }
+ control.25 {
+ iface MIXER
+ name 'HP PGA Bypass Volume'
+ value.0 71
+ value.1 71
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 -2350
+ dbvalue.1 -2350
+ }
+ }
+ control.26 {
+ iface MIXER
+ name 'HP DAC Playback Volume'
+ value.0 71
+ value.1 71
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 -2350
+ dbvalue.1 -2350
+ }
+ }
+ control.27 {
+ iface MIXER
+ name 'HPCOM Line2 Bypass Volume'
+ value.0 71
+ value.1 71
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 -2350
+ dbvalue.1 -2350
+ }
+ }
+ control.28 {
+ iface MIXER
+ name 'HPCOM PGA Bypass Volume'
+ value.0 71
+ value.1 71
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 -2350
+ dbvalue.1 -2350
+ }
+ }
+ control.29 {
+ iface MIXER
+ name 'HPCOM DAC Playback Volume'
+ value.0 71
+ value.1 71
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 118'
+ dbmin -9999999
+ dbmax 0
+ dbvalue.0 -2350
+ dbvalue.1 -2350
+ }
+ }
+ control.30 {
+ iface MIXER
+ name 'Line Playback Switch'
+ value.0 true
+ value.1 true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.31 {
+ iface MIXER
+ name 'HP Playback Switch'
+ value.0 true
+ value.1 true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.32 {
+ iface MIXER
+ name 'HPCOM Playback Switch'
+ value.0 true
+ value.1 true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.33 {
+ iface MIXER
+ name 'AGC Switch'
+ value.0 false
+ value.1 false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.34 {
+ iface MIXER
+ name 'Left AGC Target level'
+ value '-5.5dB'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 '-5.5dB'
+ item.1 '-8dB'
+ item.2 '-10dB'
+ item.3 '-12dB'
+ item.4 '-14dB'
+ item.5 '-17dB'
+ item.6 '-20dB'
+ item.7 '-24dB'
+ }
+ }
+ control.35 {
+ iface MIXER
+ name 'Right AGC Target level'
+ value '-5.5dB'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 '-5.5dB'
+ item.1 '-8dB'
+ item.2 '-10dB'
+ item.3 '-12dB'
+ item.4 '-14dB'
+ item.5 '-17dB'
+ item.6 '-20dB'
+ item.7 '-24dB'
+ }
+ }
+ control.36 {
+ iface MIXER
+ name 'Left AGC Attack time'
+ value '8ms'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 '8ms'
+ item.1 '11ms'
+ item.2 '16ms'
+ item.3 '20ms'
+ }
+ }
+ control.37 {
+ iface MIXER
+ name 'Right AGC Attack time'
+ value '8ms'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 '8ms'
+ item.1 '11ms'
+ item.2 '16ms'
+ item.3 '20ms'
+ }
+ }
+ control.38 {
+ iface MIXER
+ name 'Left AGC Decay time'
+ value '100ms'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 '100ms'
+ item.1 '200ms'
+ item.2 '400ms'
+ item.3 '500ms'
+ }
+ }
+ control.39 {
+ iface MIXER
+ name 'Right AGC Decay time'
+ value '100ms'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 '100ms'
+ item.1 '200ms'
+ item.2 '400ms'
+ item.3 '500ms'
+ }
+ }
+ control.40 {
+ iface MIXER
+ name 'De-emphasis Switch'
+ value.0 false
+ value.1 false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.41 {
+ iface MIXER
+ name 'PGA Capture Volume'
+ value.0 32
+ value.1 32
+ comment {
+ access 'read write'
+ type INTEGER
+ count 2
+ range '0 - 119'
+ dbmin 0
+ dbmax 5950
+ dbvalue.0 1600
+ dbvalue.1 1600
+ }
+ }
+ control.42 {
+ iface MIXER
+ name 'PGA Capture Switch'
+ value.0 true
+ value.1 true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 2
+ }
+ }
+ control.43 {
+ iface MIXER
+ name 'ADC HPF Cut-off'
+ value.0 Disabled
+ value.1 Disabled
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 2
+ item.0 Disabled
+ item.1 '0.0045xFs'
+ item.2 '0.0125xFs'
+ item.3 '0.025xFs'
+ }
+ }
+ control.44 {
+ iface MIXER
+ name 'Right HPCOM Mixer Line2L Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.45 {
+ iface MIXER
+ name 'Right HPCOM Mixer PGAL Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.46 {
+ iface MIXER
+ name 'Right HPCOM Mixer DACL1 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.47 {
+ iface MIXER
+ name 'Right HPCOM Mixer Line2R Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.48 {
+ iface MIXER
+ name 'Right HPCOM Mixer PGAR Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.49 {
+ iface MIXER
+ name 'Right HPCOM Mixer DACR1 Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.50 {
+ iface MIXER
+ name 'Left HPCOM Mixer Line2L Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.51 {
+ iface MIXER
+ name 'Left HPCOM Mixer PGAL Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.52 {
+ iface MIXER
+ name 'Left HPCOM Mixer DACL1 Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.53 {
+ iface MIXER
+ name 'Left HPCOM Mixer Line2R Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.54 {
+ iface MIXER
+ name 'Left HPCOM Mixer PGAR Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.55 {
+ iface MIXER
+ name 'Left HPCOM Mixer DACR1 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.56 {
+ iface MIXER
+ name 'Right HP Mixer Line2L Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.57 {
+ iface MIXER
+ name 'Right HP Mixer PGAL Bypass Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.58 {
+ iface MIXER
+ name 'Right HP Mixer DACL1 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.59 {
+ iface MIXER
+ name 'Right HP Mixer Line2R Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.60 {
+ iface MIXER
+ name 'Right HP Mixer PGAR Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.61 {
+ iface MIXER
+ name 'Right HP Mixer DACR1 Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.62 {
+ iface MIXER
+ name 'Left HP Mixer Line2L Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.63 {
+ iface MIXER
+ name 'Left HP Mixer PGAL Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.64 {
+ iface MIXER
+ name 'Left HP Mixer DACL1 Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.65 {
+ iface MIXER
+ name 'Left HP Mixer Line2R Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.66 {
+ iface MIXER
+ name 'Left HP Mixer PGAR Bypass Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.67 {
+ iface MIXER
+ name 'Left HP Mixer DACR1 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.68 {
+ iface MIXER
+ name 'Right Line Mixer Line2L Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.69 {
+ iface MIXER
+ name 'Right Line Mixer PGAL Bypass Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.70 {
+ iface MIXER
+ name 'Right Line Mixer DACL1 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.71 {
+ iface MIXER
+ name 'Right Line Mixer Line2R Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.72 {
+ iface MIXER
+ name 'Right Line Mixer PGAR Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.73 {
+ iface MIXER
+ name 'Right Line Mixer DACR1 Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.74 {
+ iface MIXER
+ name 'Left Line Mixer Line2L Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.75 {
+ iface MIXER
+ name 'Left Line Mixer PGAL Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.76 {
+ iface MIXER
+ name 'Left Line Mixer DACL1 Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.77 {
+ iface MIXER
+ name 'Left Line Mixer Line2R Bypass Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.78 {
+ iface MIXER
+ name 'Left Line Mixer PGAR Bypass Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.79 {
+ iface MIXER
+ name 'Left Line Mixer DACR1 Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.80 {
+ iface MIXER
+ name 'Right Line2R Mux'
+ value single-ended
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 single-ended
+ item.1 differential
+ }
+ }
+ control.81 {
+ iface MIXER
+ name 'Right Line1R Mux'
+ value single-ended
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 single-ended
+ item.1 differential
+ }
+ }
+ control.82 {
+ iface MIXER
+ name 'Right Line1L Mux'
+ value single-ended
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 single-ended
+ item.1 differential
+ }
+ }
+ control.83 {
+ iface MIXER
+ name 'Right PGA Mixer Line1R Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.84 {
+ iface MIXER
+ name 'Right PGA Mixer Line1L Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.85 {
+ iface MIXER
+ name 'Right PGA Mixer Line2R Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.86 {
+ iface MIXER
+ name 'Right PGA Mixer Mic3L Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.87 {
+ iface MIXER
+ name 'Right PGA Mixer Mic3R Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.88 {
+ iface MIXER
+ name 'Left Line2L Mux'
+ value single-ended
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 single-ended
+ item.1 differential
+ }
+ }
+ control.89 {
+ iface MIXER
+ name 'Left Line1R Mux'
+ value single-ended
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 single-ended
+ item.1 differential
+ }
+ }
+ control.90 {
+ iface MIXER
+ name 'Left Line1L Mux'
+ value single-ended
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 single-ended
+ item.1 differential
+ }
+ }
+ control.91 {
+ iface MIXER
+ name 'Left PGA Mixer Line1L Switch'
+ value true
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.92 {
+ iface MIXER
+ name 'Left PGA Mixer Line1R Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.93 {
+ iface MIXER
+ name 'Left PGA Mixer Line2L Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.94 {
+ iface MIXER
+ name 'Left PGA Mixer Mic3L Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.95 {
+ iface MIXER
+ name 'Left PGA Mixer Mic3R Switch'
+ value false
+ comment {
+ access 'read write'
+ type BOOLEAN
+ count 1
+ }
+ }
+ control.96 {
+ iface MIXER
+ name 'Right HPCOM Mux'
+ value 'differential of HPROUT'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'differential of HPROUT'
+ item.1 'constant VCM'
+ item.2 single-ended
+ item.3 'differential of HPLCOM'
+ item.4 'external feedback'
+ }
+ }
+ control.97 {
+ iface MIXER
+ name 'Right DAC Mux'
+ value DAC_R1
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 DAC_R1
+ item.1 DAC_R3
+ item.2 DAC_R2
+ }
+ }
+ control.98 {
+ iface MIXER
+ name 'Left HPCOM Mux'
+ value 'differential of HPLOUT'
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 'differential of HPLOUT'
+ item.1 'constant VCM'
+ item.2 single-ended
+ }
+ }
+ control.99 {
+ iface MIXER
+ name 'Left DAC Mux'
+ value DAC_L1
+ comment {
+ access 'read write'
+ type ENUMERATED
+ count 1
+ item.0 DAC_L1
+ item.1 DAC_L3
+ item.2 DAC_L2
+ }
+ }
+}
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp/0002-phycore-update.patch b/dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp/0002-phycore-update.patch
new file mode 100644
index 0000000..32f964d
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp/0002-phycore-update.patch
@@ -0,0 +1,547 @@
+diff --git a/fdts/phycore-stm32mp1-1.dts b/fdts/phycore-stm32mp1-1.dts
+new file mode 100644
+index 0000000..e3076b3
+--- /dev/null
++++ b/fdts/phycore-stm32mp1-1.dts
+@@ -0,0 +1,16 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) Phytec GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++/dts-v1/;
++
++#include "phycore-stm32mp1-1.dtsi"
++
++/ {
++ model = "PHYTEC phyCORE-STM32MP1 Dev Board";
++ compatible = "st,phycore-stm32mp1", "st,stm32mp157";
++
++};
++
+diff --git a/fdts/phycore-stm32mp1-1.dtsi b/fdts/phycore-stm32mp1-1.dtsi
+new file mode 100644
+index 0000000..4db6e5d
+--- /dev/null
++++ b/fdts/phycore-stm32mp1-1.dtsi
+@@ -0,0 +1,497 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) Phytec GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++/dts-v1/;
++
++#include "stm32mp157c.dtsi"
++#include "stm32mp157cac-pinctrl.dtsi"
++
++/ {
++
++ aliases {
++ serial0 = &uart4;
++ serial1 = &usart3;
++ serial2 = &uart7;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++};
++
++&clk_hse {
++ st,digbypass;
++};
++
++&i2c4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c4_pins_a>;
++ i2c-scl-rising-time-ns = <185>;
++ i2c-scl-falling-time-ns = <20>;
++ status = "okay";
++
++ pmic: stpmic@33 {
++ compatible = "st,stpmic1";
++ reg = <0x33>;
++ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ status = "okay";
++
++ st,main-control-register = <0x04>;
++ st,vin-control-register = <0xc0>;
++ st,usb-control-register = <0x20>;
++
++ regulators {
++ compatible = "st,stpmic1-regulators";
++
++ ldo1-supply = <&v3v3>;
++ ldo2-supply = <&v3v3>;
++ ldo3-supply = <&vdd_ddr>;
++ ldo5-supply = <&v3v3>;
++ ldo6-supply = <&v3v3>;
++
++ vddcore: buck1 {
++ regulator-name = "vddcore";
++ regulator-min-microvolt = <1200000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-always-on;
++ regulator-initial-mode = <0>;
++ regulator-over-current-protection;
++ };
++
++ vdd_ddr: buck2 {
++ regulator-name = "vdd_ddr";
++ regulator-min-microvolt = <1350000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-always-on;
++ regulator-initial-mode = <0>;
++ regulator-over-current-protection;
++ };
++
++ vdd: buck3 {
++ regulator-name = "vdd";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ st,mask-reset;
++ regulator-initial-mode = <0>;
++ regulator-over-current-protection;
++ };
++
++ v3v3: buck4 {
++ regulator-name = "v3v3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ regulator-over-current-protection;
++ regulator-initial-mode = <0>;
++ };
++
++ v1v8_audio: ldo1 {
++ regulator-name = "v1v8_audio";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ };
++
++ vdd_eth_2v5: ldo2 {
++ regulator-name = "vdd_eth_2v5";
++ regulator-min-microvolt = <2500000>;
++ regulator-max-microvolt = <2500000>;
++ regulator-always-on;
++ };
++
++ vtt_ddr: ldo3 {
++ regulator-name = "vtt_ddr";
++ regulator-min-microvolt = <500000>;
++ regulator-max-microvolt = <750000>;
++ regulator-always-on;
++ regulator-over-current-protection;
++ };
++
++ vdd_usb: ldo4 {
++ regulator-name = "vdd_usb";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ vdda: ldo5 {
++ regulator-name = "vdda";
++ regulator-min-microvolt = <2900000>;
++ regulator-max-microvolt = <2900000>;
++ regulator-boot-on;
++ };
++
++ vdd_eth_1v0: ldo6 {
++ regulator-name = "vdd_eth_1v0";
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <1000000>;
++ regulator-always-on;
++ };
++
++ vref_ddr: vref_ddr {
++ regulator-name = "vref_ddr";
++ regulator-always-on;
++ regulator-over-current-protection;
++ };
++ };
++ };
++};
++
++&iwdg2 {
++ timeout-sec = <32>;
++ status = "okay";
++};
++
++&pwr {
++ pwr-supply = <&vdd>;
++};
++
++&rng1 {
++ status = "okay";
++};
++
++&rtc {
++ status = "okay";
++};
++
++&qspi {
++ pinctrl-names = "default";
++ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
++ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ flash0: n25q128@0 {
++ compatible = "micron,n25q128a13", "jedec,spi-nor";
++ reg = <0>;
++ spi-rx-bus-width = <4>;
++ spi-max-frequency = <50000000>;
++ m25p,fast-read;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ };
++};
++
++&sdmmc1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc1_b4_pins_a>;
++ broken-cd;
++ st,neg-edge;
++ bus-width = <4>;
++ max-frequency = <10000000>;
++ vmmc-supply = <&v3v3>;
++ status = "okay";
++};
++
++&sdmmc2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
++ non-removable;
++ no-sd;
++ no-sdio;
++ st,neg-edge;
++ bus-width = <8>;
++ vmmc-supply = <&v3v3>;
++ vqmmc-supply = <&v3v3>;
++ mmc-ddr-3_3v;
++ status = "okay";
++};
++
++&uart4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart4_pins_a>;
++ status = "okay";
++};
++
++&uart7 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart7_pins_a>;
++ status = "disabled";
++};
++
++&usart3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&usart3_pins_b>;
++ status = "disabled";
++};
++
++
++/* ATF Specific */
++#include <dt-bindings/clock/stm32mp1-clksrc.h>
++#include <dt-bindings/power/stm32mp1-power.h>
++#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
++#include "stm32mp157c-security.dtsi"
++
++/ {
++ aliases {
++ gpio0 = &gpioa;
++ gpio1 = &gpiob;
++ gpio2 = &gpioc;
++ gpio3 = &gpiod;
++ gpio4 = &gpioe;
++ gpio5 = &gpiof;
++ gpio6 = &gpiog;
++ gpio7 = &gpioh;
++ gpio8 = &gpioi;
++ gpio25 = &gpioz;
++ i2c3 = &i2c4;
++ };
++};
++
++/* CLOCK init */
++&rcc {
++ secure-status = "okay";
++ st,hsi-cal;
++ st,csi-cal;
++ st,cal-sec = <60>;
++ st,clksrc = <
++ CLK_MPU_PLL1P
++ CLK_AXI_PLL2P
++ CLK_MCU_PLL3P
++ CLK_PLL12_HSE
++ CLK_PLL3_HSE
++ CLK_PLL4_HSE
++ CLK_RTC_LSE
++ CLK_MCO1_DISABLED
++ CLK_MCO2_DISABLED
++ >;
++
++ st,clkdiv = <
++ 1 /*MPU*/
++ 0 /*AXI*/
++ 0 /*MCU*/
++ 1 /*APB1*/
++ 1 /*APB2*/
++ 1 /*APB3*/
++ 1 /*APB4*/
++ 2 /*APB5*/
++ 23 /*RTC*/
++ 0 /*MCO1*/
++ 0 /*MCO2*/
++ >;
++
++ st,pkcs = <
++ CLK_CKPER_HSE
++ CLK_FMC_ACLK
++ CLK_QSPI_ACLK
++ CLK_ETH_DISABLED
++ CLK_SDMMC12_PLL4P
++ CLK_DSI_DSIPLL
++ CLK_STGEN_HSE
++ CLK_USBPHY_HSE
++ CLK_SPI2S1_PLL3Q
++ CLK_SPI2S23_PLL3Q
++ CLK_SPI45_HSI
++ CLK_SPI6_HSI
++ CLK_I2C46_HSI
++ CLK_SDMMC3_PLL4P
++ CLK_USBO_USBPHY
++ CLK_ADC_CKPER
++ CLK_CEC_LSE
++ CLK_I2C12_HSI
++ CLK_I2C35_HSI
++ CLK_UART1_HSI
++ CLK_UART24_HSI
++ CLK_UART35_HSI
++ CLK_UART6_HSI
++ CLK_UART78_HSI
++ CLK_SPDIF_PLL4P
++ CLK_FDCAN_PLL4Q
++ CLK_SAI1_PLL3Q
++ CLK_SAI2_PLL3Q
++ CLK_SAI3_PLL3Q
++ CLK_SAI4_PLL3Q
++ CLK_RNG1_LSI
++ CLK_RNG2_LSI
++ CLK_LPTIM1_PCLK1
++ CLK_LPTIM23_PCLK3
++ CLK_LPTIM45_LSE
++ >;
++
++ /* VCO = 1300.0 MHz => P = 650 (CPU) */
++ pll1: st,pll@0 {
++ cfg = < 2 80 0 0 0 PQR(1,0,0) >;
++ frac = < 0x800 >;
++ };
++
++ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
++ pll2: st,pll@1 {
++ cfg = < 2 65 1 0 0 PQR(1,1,1) >;
++ frac = < 0x1400 >;
++ };
++
++ /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
++ pll3: st,pll@2 {
++ cfg = < 1 33 1 16 36 PQR(1,1,1) >;
++ frac = < 0x1a04 >;
++ };
++
++ /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
++ pll4: st,pll@3 {
++ cfg = < 3 98 5 7 7 PQR(1,1,1) >;
++ };
++};
++
++/* Security specific */
++&etzpc {
++ st,decprot = <
++ DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
++ DECPROT(STM32MP1_ETZPC_SPI6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
++ DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
++ DECPROT(STM32MP1_ETZPC_I2C6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
++ DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
++ DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
++ DECPROT(STM32MP1_ETZPC_CRYP1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
++ >;
++};
++
++&iwdg2 {
++ secure-status = "okay";
++};
++
++&pwr {
++ system_suspend_supported_soc_modes = <
++ STM32_PM_CSLEEP_RUN
++ STM32_PM_CSTOP_ALLOW_LP_STOP
++ STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR
++ >;
++
++ system_off_soc_mode = <STM32_PM_CSTOP_ALLOW_STANDBY_DDR_OFF>;
++};
++
++&timers15 {
++ secure-status = "okay";
++ st,hsi-cal-input = <7>;
++ st,csi_cal-input = <8>;
++};
++
++/* Low-power states of regulators */
++&vddcore {
++ lp-stop {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1200000>;
++ };
++ standby-ddr-sr {
++ regulator-off-in-suspend;
++ };
++ standby-ddr-off {
++ regulator-off-in-suspend;
++ };
++};
++
++&vdd_ddr {
++ lp-stop {
++ regulator-suspend-microvolt = <1350000>;
++ regulator-on-in-suspend;
++ };
++ standby-ddr-sr {
++ regulator-suspend-microvolt = <1350000>;
++ regulator-on-in-suspend;
++ };
++ standby-ddr-off {
++ regulator-off-in-suspend;
++ };
++};
++
++&vdd {
++ lp-stop {
++ regulator-suspend-microvolt = <3300000>;
++ regulator-on-in-suspend;
++ };
++ standby-ddr-sr {
++ regulator-suspend-microvolt = <3300000>;
++ regulator-on-in-suspend;
++ };
++ standby-ddr-off {
++ regulator-suspend-microvolt = <3300000>;
++ regulator-on-in-suspend;
++ };
++};
++
++&v3v3 {
++ lp-stop {
++ regulator-suspend-microvolt = <3300000>;
++ regulator-on-in-suspend;
++ };
++ standby-ddr-sr {
++ regulator-off-in-suspend;
++ };
++ standby-ddr-off {
++ regulator-off-in-suspend;
++ };
++};
++
++&v1v8_audio {
++ standby-ddr-sr {
++ regulator-off-in-suspend;
++ };
++ standby-ddr-off {
++ regulator-off-in-suspend;
++ };
++};
++
++&vdd_eth_2v5 {
++ standby-ddr-sr {
++ regulator-off-in-suspend;
++ };
++ standby-ddr-off {
++ regulator-off-in-suspend;
++ };
++};
++
++&vtt_ddr {
++ lp-stop {
++ regulator-off-in-suspend;
++ };
++ standby-ddr-sr {
++ regulator-off-in-suspend;
++ };
++ standby-ddr-off {
++ regulator-off-in-suspend;
++ };
++};
++
++&vdd_usb {
++ standby-ddr-sr {
++ regulator-off-in-suspend;
++ };
++ standby-ddr-off {
++ regulator-off-in-suspend;
++ };
++};
++
++&vdda {
++ standby-ddr-sr {
++ regulator-off-in-suspend;
++ };
++ standby-ddr-off {
++ regulator-off-in-suspend;
++ };
++};
++
++&vdd_eth_1v0 {
++ standby-ddr-sr {
++ regulator-off-in-suspend;
++ };
++ standby-ddr-off {
++ regulator-off-in-suspend;
++ };
++};
++
++&vref_ddr {
++ lp-stop {
++ regulator-on-in-suspend;
++ };
++ standby-ddr-sr {
++ regulator-on-in-suspend;
++ };
++ standby-ddr-off {
++ regulator-off-in-suspend;
++ };
++};
+diff --git a/fdts/stm32mp157-pinctrl.dtsi b/fdts/stm32mp157-pinctrl.dtsi
+index 8037e4f..601962a 100644
+--- a/fdts/stm32mp157-pinctrl.dtsi
++++ b/fdts/stm32mp157-pinctrl.dtsi
+@@ -184,7 +184,7 @@
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
++ <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <1>;
+@@ -262,7 +262,7 @@
+
+ uart4_pins_a: uart4-0 {
+ pins1 {
+- pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
++ pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp/0003-fix-emmc-pinmux-phycore-usage.patch b/dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp/0003-fix-emmc-pinmux-phycore-usage.patch
new file mode 100644
index 0000000..b444eff
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp/0003-fix-emmc-pinmux-phycore-usage.patch
@@ -0,0 +1,13 @@
+diff --git a/fdts/stm32mp157-pinctrl.dtsi b/fdts/stm32mp157-pinctrl.dtsi
+index d1f2f6a..a259473 100644
+--- a/fdts/stm32mp157-pinctrl.dtsi
++++ b/fdts/stm32mp157-pinctrl.dtsi
+@@ -252,7 +252,7 @@
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+- <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
++ <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp/0004-fix-internal-eth-clk-pll4.patch b/dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp/0004-fix-internal-eth-clk-pll4.patch
new file mode 100644
index 0000000..23afb7f
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp/0004-fix-internal-eth-clk-pll4.patch
@@ -0,0 +1,25 @@
+diff --git a/fdts/phycore-stm32mp1-1.dtsi b/fdts/phycore-stm32mp1-1.dtsi
+index 1e3e165..6af04d0 100644
+--- a/fdts/phycore-stm32mp1-1.dtsi
++++ b/fdts/phycore-stm32mp1-1.dtsi
+@@ -280,7 +280,7 @@
+ CLK_CKPER_HSE
+ CLK_FMC_ACLK
+ CLK_QSPI_ACLK
+- CLK_ETH_DISABLED
++ CLK_ETH_PLL4P
+ CLK_SDMMC12_PLL4P
+ CLK_DSI_DSIPLL
+ CLK_STGEN_HSE
+@@ -332,9 +332,9 @@
+ frac = < 0x1a04 >;
+ };
+
+- /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
++ /* VCO = 750.0 MHz, P=125, Q=62.5, R=62.5 */
+ pll4: st,pll@3 {
+- cfg = < 3 98 5 7 7 PQR(1,1,1) >;
++ cfg = <3 124 5 11 11 PQR(1,1,1)>;
+ };
+ };
+
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp_%.bbappend b/dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp_%.bbappend
new file mode 100644
index 0000000..dcc713a
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-bsp/trusted-firmware-a/tf-a-stm32mp_%.bbappend
@@ -0,0 +1,7 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+
+SRC_URI += " \
+ file://0002-phycore-update.patch \
+ file://0003-fix-emmc-pinmux-phycore-usage.patch \
+ file://0004-fix-internal-eth-clk-pll4.patch \
+"
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp-extlinux.bb b/dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp-extlinux.bb
new file mode 100644
index 0000000..fd2f1f7
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp-extlinux.bb
@@ -0,0 +1,40 @@
+SUMMARY = "Provide 'extlinux.conf' file for U-Boot"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+
+DEPENDS += "u-boot-mkimage-native"
+
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+SRC_URI = "file://boot.scr.cmd"
+
+PV = "2.0"
+
+inherit kernel-arch extlinuxconf-phycore-stm32mp
+
+B = "${WORKDIR}/build"
+
+UBOOT_EXTLINUX_BOOTSCR = "${WORKDIR}/boot.scr.cmd"
+UBOOT_EXTLINUX_BOOTSCR_IMG = "${B}/boot.scr.uimg"
+
+UBOOT_EXTLINUX_INSTALL_DIR ?= "/boot"
+
+do_compile() {
+ # Generate boot script only when multiple extlinux subdirs are set
+ if [ "$(find ${B}/* -maxdepth 0 -type d | wc -w)" -gt 1 ]; then
+ mkimage -C none -A ${UBOOT_ARCH} -T script -d ${UBOOT_EXTLINUX_BOOTSCR} ${UBOOT_EXTLINUX_BOOTSCR_IMG}
+ fi
+}
+
+do_install() {
+ install -d ${D}/${UBOOT_EXTLINUX_INSTALL_DIR}
+ # Install boot script
+ if [ -e ${UBOOT_EXTLINUX_BOOTSCR_IMG} ]; then
+ install -m 755 ${UBOOT_EXTLINUX_BOOTSCR_IMG} ${D}/${UBOOT_EXTLINUX_INSTALL_DIR}
+ fi
+ # Install extlinux files
+ if ! [ -z "$(ls -A ${B})" ]; then
+ cp -r ${B}/* ${D}/${UBOOT_EXTLINUX_INSTALL_DIR}
+ fi
+}
+FILES_${PN} = "${UBOOT_EXTLINUX_INSTALL_DIR}"
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp-extlinux/boot.scr.cmd b/dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp-extlinux/boot.scr.cmd
new file mode 100644
index 0000000..5ad9a9d
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp-extlinux/boot.scr.cmd
@@ -0,0 +1,44 @@
+# Generate boot.scr.uimg:
+# ./tools/mkimage -C none -A arm -T script -d boot.src.cmd boot.scr.uimg
+#
+
+# M4 Firmware load
+env set m4fw_name "rproc-m4-fw.elf"
+env set m4fw_addr ${kernel_addr_r}
+env set boot_m4fw 'rproc init; rproc load 0 ${m4fw_addr} ${filesize}; rproc load_rsc 0 ${m4fw_addr} ${filesize}; rproc start 0'
+
+# boot M4 Firmware when available
+env set scan_m4fw 'if test -e ${devtype} ${devnum}:${distro_bootpart} ${m4fw_name};then echo Found M4 FW $m4fw_name; if load ${devtype} ${devnum}:${distro_bootpart} ${m4fw_addr} ${m4fw_name}; then run boot_m4fw; fi; fi;'
+
+# Update DISTRO command= search in sub-directory and load M4 firmware
+env set boot_prefixes "/${boot_device}${boot_instance}_${board_name}_"
+env set boot_extlinux "run scan_m4fw;${boot_extlinux}"
+
+if test ${boot_device} = mmc; then
+ if test ${distro_bootpart} > 4; then
+ env set boot_prefixes "/mmc${boot_instance}_${board_name}-optee_"
+ fi
+
+ #start the correct exlinux.conf
+ run scan_dev_for_boot_part
+
+elif test ${boot_device} = nand; then
+
+ #start the correct exlinux.conf without remount UBI
+ run scan_dev_for_boot
+
+elif test ${boot_device} = nor; then
+
+ #SDCARD boot
+ run bootcmd_mmc0
+
+ #NAND boot
+ env set boot_prefixes "/nand0_${board_name}_"
+ run bootcmd_ubifs0
+
+ #EMMC boot
+ env set boot_prefixes "/${boot_device}${boot_instance}-mmc1_${board_name}_"
+ run bootcmd_mmc1
+fi
+
+echo SCRIPT FAILED... ${boot_prefixes}extlinux/extlinux.conf not found !
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp/0009-ARM-v2018.11-stm32mp-r2-add-phycore-stm32mp1xx-alpha1-machine.patch b/dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp/0009-ARM-v2018.11-stm32mp-r2-add-phycore-stm32mp1xx-alpha1-machine.patch
new file mode 100644
index 0000000..53441a5
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp/0009-ARM-v2018.11-stm32mp-r2-add-phycore-stm32mp1xx-alpha1-machine.patch
@@ -0,0 +1,4213 @@
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index a346021..fe3483a 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -556,7 +556,8 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
+ stm32mp157a-dk1.dtb \
+ stm32mp157c-dk2.dtb \
+ stm32mp157c-ed1.dtb \
+- stm32mp157c-ev1.dtb
++ stm32mp157c-ev1.dtb \
++ phycore-stm32mp1-1.dtb
+
+ dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
+
+diff --git a/arch/arm/dts/phycore-stm32mp157-pinctrl.dtsi b/arch/arm/dts/phycore-stm32mp157-pinctrl.dtsi
+new file mode 100644
+index 0000000..33480d0
+--- /dev/null
++++ b/arch/arm/dts/phycore-stm32mp157-pinctrl.dtsi
+@@ -0,0 +1,1594 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
++ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
++ */
++#include <dt-bindings/pinctrl/stm32-pinfunc.h>
++
++/ {
++ soc {
++ pinctrl: pin-controller@50002000 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "st,stm32mp157-pinctrl";
++ ranges = <0 0x50002000 0xa400>;
++ interrupt-parent = <&exti>;
++ st,syscfg = <&exti 0x60 0xff>;
++ hwlocks = <&hsem 0>;
++ pins-are-numbered;
++
++ gpioa: gpio@50002000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x0 0x400>;
++ clocks = <&rcc GPIOA>;
++ st,bank-name = "GPIOA";
++ status = "disabled";
++ };
++
++ gpiob: gpio@50003000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x1000 0x400>;
++ clocks = <&rcc GPIOB>;
++ st,bank-name = "GPIOB";
++ status = "disabled";
++ };
++
++ gpioc: gpio@50004000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x2000 0x400>;
++ clocks = <&rcc GPIOC>;
++ st,bank-name = "GPIOC";
++ status = "disabled";
++ };
++
++ gpiod: gpio@50005000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x3000 0x400>;
++ clocks = <&rcc GPIOD>;
++ st,bank-name = "GPIOD";
++ status = "disabled";
++ };
++
++ gpioe: gpio@50006000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x4000 0x400>;
++ clocks = <&rcc GPIOE>;
++ st,bank-name = "GPIOE";
++ status = "disabled";
++ };
++
++ gpiof: gpio@50007000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x5000 0x400>;
++ clocks = <&rcc GPIOF>;
++ st,bank-name = "GPIOF";
++ status = "disabled";
++ };
++
++ gpiog: gpio@50008000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x6000 0x400>;
++ clocks = <&rcc GPIOG>;
++ st,bank-name = "GPIOG";
++ status = "disabled";
++ };
++
++ gpioh: gpio@50009000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x7000 0x400>;
++ clocks = <&rcc GPIOH>;
++ st,bank-name = "GPIOH";
++ status = "disabled";
++ };
++
++ gpioi: gpio@5000a000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x8000 0x400>;
++ clocks = <&rcc GPIOI>;
++ st,bank-name = "GPIOI";
++ status = "disabled";
++ };
++
++ gpioj: gpio@5000b000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x9000 0x400>;
++ clocks = <&rcc GPIOJ>;
++ st,bank-name = "GPIOJ";
++ status = "disabled";
++ };
++
++ gpiok: gpio@5000c000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0xa000 0x400>;
++ clocks = <&rcc GPIOK>;
++ st,bank-name = "GPIOK";
++ status = "disabled";
++ };
++
++ adc1_in6_pins_a: adc1-in6 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
++ };
++ };
++
++ adc12_ain_pins_a: adc12-ain-0 {
++ pins {
++ pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
++ <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
++ <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
++ <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
++ };
++ };
++
++ adc12_usb_pwr_pins_a: adc12-usb-pwr-pins-0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
++ <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
++ };
++ };
++
++ cec_pins_a: cec-0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 15, AF4)>;
++ bias-disable;
++ drive-open-drain;
++ slew-rate = <0>;
++ };
++ };
++
++ cec_pins_sleep_a: cec-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
++ };
++ };
++
++ cec_pins_b: cec-1 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 6, AF5)>;
++ bias-disable;
++ drive-open-drain;
++ slew-rate = <0>;
++ };
++ };
++
++ cec_pins_sleep_b: cec-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
++ };
++ };
++
++ dac_ch1_pins_a: dac-ch1 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
++ };
++ };
++
++ dac_ch2_pins_a: dac-ch2 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
++ };
++ };
++
++ dcmi_pins_a: dcmi-0 {
++ pins {
++ pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
++ <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
++ <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
++ <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
++ <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
++ <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
++ <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
++ <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
++ <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
++ <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
++ <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
++ <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
++ <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
++ <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
++ <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
++ bias-disable;
++ };
++ };
++
++ dcmi_sleep_pins_a: dcmi-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
++ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
++ <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
++ <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
++ <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
++ <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
++ <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
++ <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
++ <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
++ <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
++ <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
++ <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
++ <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
++ <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
++ <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
++ };
++ };
++
++ dfsdm_clkout_pins_a: dfsdm-clkout-pins-0 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 13, AF3)>; /* DFSDM_CKOUT */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++ };
++
++ dfsdm_clkout_sleep_pins_a: dfsdm-clkout-sleep-pins-0 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 13, ANALOG)>; /* DFSDM_CKOUT */
++ };
++ };
++
++ dfsdm_data1_pins_a: dfsdm-data1-pins-0 {
++ pins {
++ pinmux = <STM32_PINMUX('C', 3, AF3)>; /* DFSDM_DATA1 */
++ };
++ };
++
++ dfsdm_data1_sleep_pins_a: dfsdm-data1-sleep-pins-0 {
++ pins {
++ pinmux = <STM32_PINMUX('C', 3, ANALOG)>; /* DFSDM_DATA1 */
++ };
++ };
++
++ dfsdm_data3_pins_a: dfsdm-data3-pins-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 13, AF6)>; /* DFSDM_DATA3 */
++ };
++ };
++
++ dfsdm_data3_sleep_pins_a: dfsdm-data3-sleep-pins-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 13, ANALOG)>; /* DFSDM_DATA3 */
++ };
++ };
++
++ ethernet0_rgmii_pins_a: rgmii-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
++ <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
++ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
++ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
++ <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
++ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
++ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
++ <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
++ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
++ <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
++ <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
++ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
++ <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
++ bias-disable;
++ };
++ };
++
++ ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
++ <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
++ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
++ <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
++ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
++ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
++ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
++ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
++ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
++ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
++ <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
++ <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
++ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
++ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
++ };
++ };
++
++ fmc_pins_a: fmc-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
++ <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
++ <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
++ <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
++ <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
++ <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
++ <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
++ <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
++ <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
++ <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
++ <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
++ <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
++ <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
++ bias-pull-up;
++ };
++ };
++
++ fmc_sleep_pins_a: fmc-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
++ <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
++ <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
++ <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
++ <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
++ <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
++ <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
++ <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
++ <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
++ <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
++ <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
++ <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
++ <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
++ <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
++ };
++ };
++
++ hdp0_pins_a: hdp0-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 12, AF2)>; /* HDP0 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp0_pins_sleep_a: hdp0-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 12, ANALOG)>; /* HDP0 */
++ };
++ };
++
++ hdp0_pins_b: hdp0-1 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 10, AF0)>; /* HDP0 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp0_pins_sleep_b: hdp0-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 10, ANALOG)>; /* HDP0 */
++ };
++ };
++
++ hdp1_pins_a: hdp1-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 13, AF2)>; /* HDP1 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp1_pins_sleep_a: hdp1-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 13, ANALOG)>; /* HDP1 */
++ };
++ };
++
++ hdp1_pins_b: hdp1-1 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 9, AF0)>; /* HDP1 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp1_pins_sleep_b: hdp1-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 9, ANALOG)>; /* HDP1 */
++ };
++ };
++
++ hdp2_pins_a: hdp2-0 {
++ pins {
++ pinmux = <STM32_PINMUX('J', 5, AF2)>; /* HDP2 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp2_pins_sleep_a: hdp2-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('J', 5, ANALOG)>; /* HDP2 */
++ };
++ };
++
++ hdp2_pins_b: hdp2-1 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 13, AF0)>; /* HDP2 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp2_pins_sleep_b: hdp2-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 13, ANALOG)>; /* HDP2 */
++ };
++ };
++
++ hdp3_pins_a: hdp3-0 {
++ pins {
++ pinmux = <STM32_PINMUX('J', 6, AF2)>; /* HDP3 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp3_pins_sleep_a: hdp3-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('J', 6, ANALOG)>; /* HDP3 */
++ };
++ };
++
++ hdp3_pins_b: hdp3-1 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 15, AF0)>; /* HDP3 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp3_pins_sleep_b: hdp3-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 15, ANALOG)>; /* HDP3 */
++ };
++ };
++
++ hdp4_pins_a: hdp4-0 {
++ pins {
++ pinmux = <STM32_PINMUX('K', 1, AF2)>; /* HDP4 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp4_pins_sleep_a: hdp4-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('K', 1, ANALOG)>; /* HDP4 */
++ };
++ };
++
++ hdp4_pins_b: hdp4-1 {
++ pins {
++ pinmux = <STM32_PINMUX('C', 7, AF0)>; /* HDP4 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp4_pins_sleep_b: hdp4-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* HDP4 */
++ };
++ };
++
++ hdp5_pins_a: hdp5-0 {
++ pins {
++ pinmux = <STM32_PINMUX('K', 2, AF2)>; /* HDP5 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp5_pins_sleep_a: hdp5-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('K', 2, ANALOG)>; /* HDP5 */
++ };
++ };
++
++ hdp5_pins_b: hdp5-1 {
++ pins {
++ pinmux = <STM32_PINMUX('D', 3, AF0)>; /* HDP5 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp5_pins_sleep_b: hdp5-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('D', 3, ANALOG)>; /* HDP5 */
++ };
++ };
++
++ hdp6_pins_a: hdp6-0 {
++ pins {
++ pinmux = <STM32_PINMUX('K', 5, AF2)>; /* HDP6 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp6_pins_sleep_a: hdp6-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('K', 5, ANALOG)>; /* HDP6 */
++ };
++ };
++
++ hdp6_pins_b: hdp6-1 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 8, AF0)>; /* HDP6 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp6_pins_sleep_b: hdp6-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 8, ANALOG)>; /* HDP6 */
++ };
++ };
++
++ hdp7_pins_a: hdp7-0 {
++ pins {
++ pinmux = <STM32_PINMUX('K', 6, AF2)>; /* HDP7 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp7_pins_sleep_a: hdp7-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('K', 6, ANALOG)>; /* HDP7 */
++ };
++ };
++
++ hdp7_pins_b: hdp7-1 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 9, AF0)>; /* HDP7 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp7_pins_sleep_b: hdp7-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* HDP7 */
++ };
++ };
++
++ i2c1_pins_a: i2c1-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
++ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
++ bias-disable;
++ drive-open-drain;
++ slew-rate = <0>;
++ };
++ };
++
++ i2c1_pins_sleep_a: i2c1-1 {
++ pins {
++ pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
++ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
++ };
++ };
++
++ i2c2_pins_a: i2c2-0 {
++ pins {
++ pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
++ <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
++ bias-disable;
++ drive-open-drain;
++ slew-rate = <0>;
++ };
++ };
++
++ i2c2_pins_sleep_a: i2c2-1 {
++ pins {
++ pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
++ <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
++ };
++ };
++
++ i2s2_pins_a: i2s2-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
++ <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
++ <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-disable;
++ };
++ };
++
++ i2s2_pins_sleep_a: i2s2-1 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
++ <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
++ <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
++ };
++ };
++
++ ltdc_pins_a: ltdc-a-0 {
++ pins {
++ pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
++ <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
++ <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
++ <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */
++ <STM32_PINMUX('C', 10, AF14)>, /* LCD_R2 */
++ <STM32_PINMUX('B', 0, AF9)>, /* LCD_R3 */
++ <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
++ <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */
++ <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
++ <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
++ <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
++ <STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */
++ <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
++ <STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */
++ <STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */
++ <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
++ <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
++ <STM32_PINMUX('G', 11, AF14)>, /* LCD_B3 */
++ <STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */
++ <STM32_PINMUX('I', 5, AF14)>, /* LCD_B5 */
++ <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
++ <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++ };
++
++ ltdc_pins_sleep_a: ltdc-a-1 {
++ pins {
++ pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
++ <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
++ <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
++ <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */
++ <STM32_PINMUX('C', 10, ANALOG)>, /* LCD_R2 */
++ <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_R3 */
++ <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
++ <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */
++ <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
++ <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
++ <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
++ <STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */
++ <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
++ <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */
++ <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */
++ <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
++ <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
++ <STM32_PINMUX('G', 11, ANALOG)>, /* LCD_B3 */
++ <STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */
++ <STM32_PINMUX('I', 5, ANALOG)>, /* LCD_B5 */
++ <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
++ <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
++ };
++ };
++
++ ltdc_pins_b: ltdc-b-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
++ <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
++ <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
++ <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
++ <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
++ <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
++ <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
++ <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
++ <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
++ <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
++ <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
++ <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
++ <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
++ <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
++ <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
++ <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
++ <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
++ <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
++ <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
++ <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
++ <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
++ <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
++ <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
++ <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
++ <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
++ <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
++ <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
++ <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++ };
++
++ ltdc_pins_sleep_b: ltdc-b-1 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
++ <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
++ <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
++ <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
++ <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
++ <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
++ <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
++ <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
++ <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
++ <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
++ <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
++ <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
++ <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
++ <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
++ <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
++ <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
++ <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
++ <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
++ <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
++ <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
++ <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
++ <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
++ <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
++ <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
++ <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
++ <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
++ <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
++ <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
++ };
++ };
++
++ m_can1_pins_a: m-can1-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
++ slew-rate = <0>;
++ drive-push-pull;
++ bias-disable;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('A', 11, AF9)>, /* CAN1_RX */
++ <STM32_PINMUX('G', 1, GPIO)>;
++ bias-disable;
++ };
++ };
++
++ m_can1_sleep_pins_a: m_can1-sleep@0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */
++ <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */
++ };
++ };
++
++ pwm1_pins_a: pwm1-0 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
++ <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */
++ <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */
++ bias-pull-down;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ };
++
++ pwm1_sleep_pins_a: pwm1-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
++ <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */
++ <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */
++ };
++ };
++
++ pwm2_pins_a: pwm2-0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
++ bias-pull-down;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ };
++
++ pwm2_sleep_pins_a: pwm2-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
++ };
++ };
++
++ pwm3_pins_a: pwm3-0 {
++ pins {
++ pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */
++ bias-pull-down;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ };
++
++ pwm3_sleep_pins_a: pwm3-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */
++ };
++ };
++
++ pwm4_pins_a: pwm4-0 {
++ pins {
++ pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
++ <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
++ bias-pull-down;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ };
++
++ pwm4_sleep_pins_a: pwm4-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
++ <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
++ };
++ };
++
++ pwm4_pins_b: pwm4-1 {
++ pins {
++ pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
++ bias-pull-down;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ };
++
++ pwm4_sleep_pins_b: pwm4-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
++ };
++ };
++
++ pwm5_pins_a: pwm5-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */
++ bias-pull-down;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ };
++
++ pwm5_sleep_pins_a: pwm5-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */
++ };
++ };
++
++ pwm8_pins_a: pwm8-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
++ bias-pull-down;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ };
++
++ pwm8_sleep_pins_a: pwm8-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */
++ };
++ };
++
++ qspi_bk1_pins_a: qspi-bk1-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
++ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
++ <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
++ <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
++ bias-pull-up;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++ };
++
++ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
++ <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
++ <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
++ <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
++ <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
++ };
++ };
++
++ qspi_clk_pins_a: qspi-clk-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <3>;
++ };
++ };
++
++ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
++ };
++ };
++
++ sai2a_pins_a: sai2a-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
++ <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
++ <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
++ <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
++ slew-rate = <0>;
++ drive-push-pull;
++ bias-disable;
++ };
++ };
++
++ sai2a_sleep_pins_a: sai2a-1 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
++ <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
++ <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
++ <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
++ };
++ };
++
++ sai2b_pins_a: sai2b-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('H', 2, AF10)>, /* SAI2_SCK_B */
++ <STM32_PINMUX('C', 0, AF8)>, /* SAI2_FS_B */
++ <STM32_PINMUX('H', 3, AF10)>; /* SAI2_MCLK_B */
++ slew-rate = <0>;
++ drive-push-pull;
++ bias-disable;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('F', 11, AF10)>, /* SAI2_SD_B */
++ <STM32_PINMUX('I', 6, AF10)>; /* SAI2_SD_A */
++ bias-disable;
++ };
++ };
++
++ sai2b_sleep_pins_a: sai2b-1 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
++ <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
++ <STM32_PINMUX('H', 2, ANALOG)>, /* SAI2_SCK_B */
++ <STM32_PINMUX('C', 0, ANALOG)>, /* SAI2_FS_B */
++ <STM32_PINMUX('H', 3, ANALOG)>; /* SAI2_MCLK_B */
++ };
++ };
++
++ sai2b_pins_b: sai2b-2 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
++ bias-disable;
++ };
++ };
++
++ sai2b_sleep_pins_b: sai2b-3 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
++ };
++ };
++
++ sai4a_pins_a: sai4a-0 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
++ slew-rate = <0>;
++ drive-push-pull;
++ bias-disable;
++ };
++ };
++
++ sai4a_sleep_pins_a: sai4a-1 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
++ };
++ };
++
++ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
++ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
++ <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
++ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
++ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-disable;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
++ slew-rate = <2>;
++ drive-push-pull;
++ bias-disable;
++ };
++ };
++
++ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
++ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
++ <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
++ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-disable;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
++ slew-rate = <2>;
++ drive-push-pull;
++ bias-disable;
++ };
++ pins3 {
++ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
++ slew-rate = <1>;
++ drive-open-drain;
++ bias-disable;
++ };
++ };
++
++ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
++ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
++ <STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC1_D2 */
++ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
++ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
++ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
++ };
++ };
++
++ sdmmc1_dir_pins_a: sdmmc1-dir-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
++ <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
++ <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ pins2{
++ pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
++ bias-pull-up;
++ };
++ };
++
++ sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
++ <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
++ <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
++ <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
++ };
++ };
++
++ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
++ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
++ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
++ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
++ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
++ slew-rate = <2>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ };
++
++ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
++ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
++ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
++ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
++ slew-rate = <2>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ pins3 {
++ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
++ slew-rate = <1>;
++ drive-open-drain;
++ bias-pull-up;
++ };
++ };
++
++ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
++ <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
++ <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
++ <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
++ <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
++ <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
++ };
++ };
++
++ sdmmc2_b4_pins_b: sdmmc2-b4-1 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
++ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
++ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
++ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
++ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-disable;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
++ slew-rate = <2>;
++ drive-push-pull;
++ bias-disable;
++ };
++ };
++
++ sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
++ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
++ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
++ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-disable;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
++ slew-rate = <2>;
++ drive-push-pull;
++ bias-disable;
++ };
++ pins3 {
++ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
++ slew-rate = <1>;
++ drive-open-drain;
++ bias-disable;
++ };
++ };
++
++ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
++ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
++ <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
++ <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ };
++
++ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
++ <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
++ <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
++ <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
++ };
++ };
++
++ sdmmc3_b4_pins_a: sdmmc3-b4-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
++ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
++ <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
++ <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
++ <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
++ slew-rate = <2>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ };
++
++ sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
++ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
++ <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
++ <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
++ slew-rate = <2>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ pins3 {
++ pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
++ slew-rate = <1>;
++ drive-open-drain;
++ bias-pull-up;
++ };
++ };
++
++ sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
++ <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
++ <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
++ <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
++ <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
++ <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
++ };
++ };
++
++ spdifrx_pins_a: spdifrx-0 {
++ pins {
++ pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
++ bias-disable;
++ };
++ };
++
++ spdifrx_sleep_pins_a: spdifrx-1 {
++ pins {
++ pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
++ };
++ };
++
++ spi4_pins_a: spi4-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
++ <STM32_PINMUX('E', 14, AF5)>; /* SPI4_MOSI */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++
++ pins2 {
++ pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
++ bias-disable;
++ };
++ };
++
++ spi4_sleep_pins_a: spi4-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 12, ANALOG)>, /* SPI4_SCK */
++ <STM32_PINMUX('E', 13, ANALOG)>, /* SPI4_MISO */
++ <STM32_PINMUX('E', 14, ANALOG)>; /* SPI4_MOSI */
++ };
++ };
++
++ spi5_pins_a: spi5-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('F', 7, AF5)>, /* SPI5_SCK */
++ <STM32_PINMUX('F', 9, AF5)>; /* SPI5_MOSI */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++
++ pins2 {
++ pinmux = <STM32_PINMUX('F', 8, AF5)>; /* SPI5_MISO */
++ bias-disable;
++ };
++ };
++
++ spi5_sleep_pins_a: spi5-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* SPI5_SCK */
++ <STM32_PINMUX('F', 8, ANALOG)>, /* SPI5_MISO */
++ <STM32_PINMUX('F', 9, ANALOG)>; /* SPI5_MOSI */
++ };
++ };
++
++ uart4_pins_a: uart4-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
++ bias-disable;
++ };
++ };
++
++ uart4_idle_pins_a: uart4-idle-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
++ bias-disable;
++ };
++ };
++
++ uart4_sleep_pins_a: uart4-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
++ <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
++ };
++ };
++
++ uart7_pins_a: uart7-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
++ bias-disable;
++ };
++ };
++
++ uart7_idle_pins_a: uart7-idle-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* USART7_TX */
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
++ bias-disable;
++ };
++ };
++
++ uart7_sleep_pins_a: uart7-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* USART7_TX */
++ <STM32_PINMUX('E', 7, ANALOG)>; /* USART7_RX */
++ };
++ };
++
++ usart3_pins_a: usart3-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
++ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
++ <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
++ bias-disable;
++ };
++ };
++
++ usart3_idle_pins_a: usart3-idle-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
++ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
++ <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
++ bias-disable;
++ };
++ };
++
++ usart3_sleep_pins_a: usart3-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
++ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
++ <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */
++ <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
++ };
++ };
++
++ usart3_pins_b: usart3-1 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
++ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
++ <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
++ bias-disable;
++ };
++ };
++
++ usart3_idle_pins_b: usart3-idle-1 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
++ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
++ <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
++ bias-disable;
++ };
++ };
++
++ usart3_sleep_pins_b: usart3-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
++ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
++ <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */
++ <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
++ };
++ };
++
++ usbotg_hs_pins_a: usbotg_hs-0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
++ };
++ };
++ };
++
++ pinctrl_z: pin-controller-z@54004000 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "st,stm32mp157-z-pinctrl";
++ ranges = <0 0x54004000 0x400>;
++ pins-are-numbered;
++ interrupt-parent = <&exti>;
++ st,syscfg = <&exti 0x60 0xff>;
++ hwlocks = <&hsem 0>;
++
++ gpioz: gpio@54004000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0 0x400>;
++ clocks = <&rcc GPIOZ>;
++ st,bank-name = "GPIOZ";
++ st,bank-ioport = <11>;
++ status = "disabled";
++ };
++
++ btreg: bt_reg_on-0 {
++ pins {
++ pinmux = <STM32_PINMUX('Z', 6, GPIO)>;
++ drive-push-pull;
++ bias-pull-up;
++ output-high;
++ slew-rate = <0>;
++ };
++ };
++
++
++ usart1_pins_a: usart1-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('Z', 7, AF7)>; /* USART1_TX */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
++ bias-disable;
++ };
++ };
++
++ usart1_idle_pins_a: usart1-idle-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('Z', 7, ANALOG)>; /* USART1_TX */
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
++ bias-disable;
++ };
++ };
++
++ usart1_sleep_pins_a: usart1-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('Z', 7, ANALOG)>, /* USART1_TX */
++ <STM32_PINMUX('Z', 6, ANALOG)>; /* USART1_RX */
++ };
++ };
++
++ i2c4_pins_a: i2c4-0 {
++ pins {
++ pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
++ <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
++ bias-disable;
++ drive-open-drain;
++ slew-rate = <0>;
++ };
++ };
++
++ i2c4_pins_sleep_a: i2c4-1 {
++ pins {
++ pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
++ <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
++ };
++ };
++
++ spi1_pins_a: spi1-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
++ <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++
++ pins2 {
++ pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
++ bias-disable;
++ };
++ };
++
++ spi1_sleep_pins_a: spi1-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */
++ <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
++ <STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */
++ };
++ };
++ };
++ };
++};
+diff --git a/arch/arm/dts/phycore-stm32mp157cac-pinctrl.dtsi b/arch/arm/dts/phycore-stm32mp157cac-pinctrl.dtsi
+new file mode 100644
+index 0000000..13d3583
+--- /dev/null
++++ b/arch/arm/dts/phycore-stm32mp157cac-pinctrl.dtsi
+@@ -0,0 +1,78 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
++ * Author: Alexandre Torgue <alexandre.torgue@st.com>
++ */
++
++#include "phycore-stm32mp157-pinctrl.dtsi"
++/ {
++ soc {
++ pinctrl: pin-controller@50002000 {
++ st,package = <STM32MP157CAC>;
++
++ gpioa: gpio@50002000 {
++ status = "okay";
++ ngpios = <16>;
++ gpio-ranges = <&pinctrl 0 0 16>;
++ };
++
++ gpiob: gpio@50003000 {
++ status = "okay";
++ ngpios = <16>;
++ gpio-ranges = <&pinctrl 0 16 16>;
++ };
++
++ gpioc: gpio@50004000 {
++ status = "okay";
++ ngpios = <16>;
++ gpio-ranges = <&pinctrl 0 32 16>;
++ };
++
++ gpiod: gpio@50005000 {
++ status = "okay";
++ ngpios = <16>;
++ gpio-ranges = <&pinctrl 0 48 16>;
++ };
++
++ gpioe: gpio@50006000 {
++ status = "okay";
++ ngpios = <16>;
++ gpio-ranges = <&pinctrl 0 64 16>;
++ };
++
++ gpiof: gpio@50007000 {
++ status = "okay";
++ ngpios = <16>;
++ gpio-ranges = <&pinctrl 0 80 16>;
++ };
++
++ gpiog: gpio@50008000 {
++ status = "okay";
++ ngpios = <16>;
++ gpio-ranges = <&pinctrl 0 96 16>;
++ };
++
++ gpioh: gpio@50009000 {
++ status = "okay";
++ ngpios = <16>;
++ gpio-ranges = <&pinctrl 0 112 16>;
++ };
++
++ gpioi: gpio@5000a000 {
++ status = "okay";
++ ngpios = <12>;
++ gpio-ranges = <&pinctrl 0 128 12>;
++ };
++ };
++
++ pinctrl_z: pin-controller-z@54004000 {
++ st,package = <STM32MP157CAC>;
++
++ gpioz: gpio@54004000 {
++ status = "okay";
++ ngpios = <8>;
++ gpio-ranges = <&pinctrl_z 0 400 8>;
++ };
++ };
++ };
++};
+diff --git a/arch/arm/dts/phycore-stm32mp157cac-som.dtsi b/arch/arm/dts/phycore-stm32mp157cac-som.dtsi
+new file mode 100644
+index 0000000..e5367e8
+--- /dev/null
++++ b/arch/arm/dts/phycore-stm32mp157cac-som.dtsi
+@@ -0,0 +1,347 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++/dts-v1/;
++
++#include "stm32mp157c.dtsi"
++#include "stm32mp157c-m4-srm.dtsi"
++#include "phycore-stm32mp157cac-pinctrl.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/mfd/st,stpmic1.h>
++#include <dt-bindings/net/ti-dp83867.h>
++#include <dt-bindings/rtc/rtc-stm32.h>
++
++
++/ {
++ model = "Phytec GmbH phycore-stm32mp1-1 SOM";
++ compatible = "phytec,PCM-068-1534-0-005", "st,stm32mp157";
++
++ memory@c0000000 {
++ reg = <0xc0000000 0x20000000>;
++ };
++
++ reserved-memory {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ retram: retram@0x38000000 {
++ compatible = "shared-dma-pool";
++ reg = <0x38000000 0x10000>;
++ no-map;
++ };
++
++ mcuram: mcuram@0x30000000 {
++ compatible = "shared-dma-pool";
++ reg = <0x30000000 0x40000>;
++ no-map;
++ };
++
++ mcuram2: mcuram2@0x10000000 {
++ compatible = "shared-dma-pool";
++ reg = <0x10000000 0x40000>;
++ no-map;
++ };
++
++ vdev0vring0: vdev0vring0@10040000 {
++ compatible = "shared-dma-pool";
++ reg = <0x10040000 0x2000>;
++ no-map;
++ };
++
++ vdev0vring1: vdev0vring1@10042000 {
++ compatible = "shared-dma-pool";
++ reg = <0x10042000 0x2000>;
++ no-map;
++ };
++
++ vdev0buffer: vdev0buffer@10044000 {
++ compatible = "shared-dma-pool";
++ reg = <0x10044000 0x4000>;
++ no-map;
++ };
++
++ gpu_reserved: gpu@dc000000 {
++ reg = <0xdc000000 0x4000000>;
++ no-map;
++ };
++ };
++
++ sram: sram@10050000 {
++ compatible = "mmio-sram";
++ reg = <0x10050000 0x10000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 0x10050000 0x10000>;
++
++ dma_pool: dma_pool@0 {
++ reg = <0x0 0x10000>;
++ pool;
++ };
++ };
++};
++
++&dma1 {
++ sram = <&dma_pool>;
++};
++
++&dma2 {
++ sram = <&dma_pool>;
++};
++
++&dts {
++ status = "okay";
++};
++
++&gpu {
++ contiguous-area = <&gpu_reserved>;
++ status = "okay";
++};
++
++&spi1 {
++ status = "disabled";
++};
++
++&i2c4 {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&i2c4_pins_a>;
++ pinctrl-1 = <&i2c4_pins_sleep_a>;
++ i2c-scl-rising-time-ns = <185>;
++ i2c-scl-falling-time-ns = <20>;
++ status = "okay";
++ /delete-property/dmas;
++ /delete-property/dma-names;
++
++ pmic: stpmic@33 {
++ compatible = "st,stpmic1";
++ reg = <0x33>;
++ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ status = "okay";
++
++ st,main-control-register = <0x04>;
++ st,vin-control-register = <0xc0>;
++ st,usb-control-register = <0x20>;
++
++ regulators {
++ compatible = "st,stpmic1-regulators";
++
++ ldo1-supply = <&v3v3>;
++ ldo2-supply = <&v3v3>;
++ ldo3-supply = <&vdd_ddr>;
++ ldo5-supply = <&v3v3>;
++ ldo6-supply = <&v3v3>;
++ pwr_sw1-supply = <&bst_out>;
++ pwr_sw2-supply = <&bst_out>;
++
++ vddcore: buck1 {
++ regulator-name = "vddcore";
++ regulator-min-microvolt = <1200000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-always-on;
++ regulator-initial-mode = <0>;
++ regulator-over-current-protection;
++ };
++
++ vdd_ddr: buck2 {
++ regulator-name = "vdd_ddr";
++ regulator-min-microvolt = <1350000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-always-on;
++ regulator-initial-mode = <0>;
++ regulator-over-current-protection;
++ };
++
++ vdd: buck3 {
++ regulator-name = "vdd";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ st,mask-reset;
++ regulator-initial-mode = <0>;
++ regulator-over-current-protection;
++ };
++
++ v3v3: buck4 {
++ regulator-name = "v3v3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ regulator-over-current-protection;
++ regulator-initial-mode = <0>;
++ };
++
++ v1v8_audio: ldo1 {
++ regulator-name = "v1v8_audio";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ interrupts = <IT_CURLIM_LDO1 0>;
++
++ };
++
++ vdd_eth_2v5: ldo2 {
++ regulator-name = "dd_eth_2v5";
++ regulator-min-microvolt = <2500000>;
++ regulator-max-microvolt = <2500000>;
++ regulator-always-on;
++ interrupts = <IT_CURLIM_LDO2 0>;
++
++ };
++
++ vtt_ddr: ldo3 {
++ regulator-name = "vtt_ddr";
++ regulator-min-microvolt = <500000>;
++ regulator-max-microvolt = <750000>;
++ regulator-always-on;
++ regulator-over-current-protection;
++ };
++
++ vdd_usb: ldo4 {
++ regulator-name = "vdd_usb";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ interrupts = <IT_CURLIM_LDO4 0>;
++ };
++
++ vdda: ldo5 {
++ regulator-name = "vdda";
++ regulator-min-microvolt = <2900000>;
++ regulator-max-microvolt = <2900000>;
++ interrupts = <IT_CURLIM_LDO5 0>;
++ regulator-boot-on;
++ };
++
++ vdd_eth_1v0: ldo6 {
++ regulator-name = "vdd_eth_1v0";
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <1000000>;
++ regulator-always-on;
++ interrupts = <IT_CURLIM_LDO6 0>;
++
++ };
++
++ vref_ddr: vref_ddr {
++ regulator-name = "vref_ddr";
++ regulator-always-on;
++ regulator-over-current-protection;
++ };
++
++ bst_out: boost {
++ regulator-name = "bst_out";
++ interrupts = <IT_OCP_BOOST 0>;
++ };
++
++ vbus_otg: pwr_sw1 {
++ regulator-name = "vbus_otg";
++ interrupts = <IT_OCP_OTG 0>;
++ regulator-active-discharge;
++ };
++
++ vbus_sw: pwr_sw2 {
++ regulator-name = "vbus_sw";
++ interrupts = <IT_OCP_SWOUT 0>;
++ regulator-active-discharge;
++ };
++ };
++
++ onkey {
++ compatible = "st,stpmic1-onkey";
++ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
++ interrupt-names = "onkey-falling", "onkey-rising";
++ status = "okay";
++ };
++
++ watchdog {
++ compatible = "st,stpmic1-wdt";
++ status = "disabled";
++ };
++ };
++
++ eeprom@50 {
++ compatible = "microchip,24c32", "atmel,24c32";
++ reg = <0x50>;
++ };
++
++ i2c4_rtc: rtc@52 {
++ compatible = "microcrystal,rv3028";
++ reg = <0x52>;
++ /*interrupt-parent = <&gpio5>;
++ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;*/
++ status = "okay";
++ };
++};
++
++&m4_rproc {
++ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
++ <&vdev0vring1>, <&vdev0buffer>;
++ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
++ mbox-names = "vq0", "vq1", "shutdown";
++ interrupt-parent = <&exti>;
++ interrupts = <68 1>;
++ interrupt-names = "wdg";
++ recovery;
++ status = "okay";
++};
++
++&ipcc {
++ status = "okay";
++};
++
++&iwdg2 {
++ timeout-sec = <32>;
++ status = "okay";
++};
++
++&pwr {
++ pwr-supply = <&vdd>;
++};
++
++&rng1 {
++ status = "okay";
++};
++
++&rtc {
++ status = "okay";
++};
++
++&qspi {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
++ pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
++ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ flash0: w25q128@0 {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-rx-bus-width = <4>;
++ spi-max-frequency = <50000000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ };
++};
++
++&sdmmc2 {
++ pinctrl-names = "default", "opendrain", "sleep";
++ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
++ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
++ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
++ non-removable;
++ no-sd;
++ no-sdio;
++ st,neg-edge;
++ bus-width = <8>;
++ vmmc-supply = <&v3v3>;
++ vqmmc-supply = <&v3v3>;
++ mmc-ddr-3_3v;
++ status = "okay";
++};
++
+diff --git a/arch/arm/dts/phycore-stm32mp1-1-a7-examples.dts b/arch/arm/dts/phycore-stm32mp1-1-a7-examples.dts
+new file mode 100644
+index 0000000..f9a68a7
+--- /dev/null
++++ b/arch/arm/dts/phycore-stm32mp1-1-a7-examples.dts
+@@ -0,0 +1,15 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++/dts-v1/;
++
++#include "phycore-stm32mp1-1.dtsi"
++#include <dt-bindings/rtc/rtc-stm32.h>
++
++/ {
++ model = "Phytec GmbH phycore-stm32mp1-1 Dev Board";
++ compatible = "phytec,pcm939-1517-1-002", "st,phycore-stm32mp1-1-a7-examples", "st,stm32mp157";
++};
+diff --git a/arch/arm/dts/phycore-stm32mp1-1-m4-examples.dts b/arch/arm/dts/phycore-stm32mp1-1-m4-examples.dts
+new file mode 100644
+index 0000000..3871191
+--- /dev/null
++++ b/arch/arm/dts/phycore-stm32mp1-1-m4-examples.dts
+@@ -0,0 +1,157 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++/dts-v1/;
++
++#include "phycore-stm32mp1-1.dtsi"
++#include <dt-bindings/rtc/rtc-stm32.h>
++
++/ {
++ model = "Phytec GmbH phycore-stm32mp1-1 Dev Board";
++ compatible = "phytec,pcm939-1517-1-002", "st,phycore-stm32mp1-1-m4-examples", "st,stm32mp157";
++};
++
++&adc {
++ status = "disabled";
++};
++
++&dac {
++ status = "disabled";
++};
++
++&dma2 {
++ status = "disabled";
++};
++
++&dmamux1 {
++ dma-masters = <&dma1>;
++ dma-channels = <8>;
++};
++
++&m4_adc {
++ vref-supply = <&vrefbuf>;
++ status = "okay";
++};
++
++&m4_dac {
++ status = "okay";
++};
++
++&m4_dma2 {
++ status = "okay";
++};
++
++&m4_crc2 {
++ status = "okay";
++};
++
++&m4_cryp2 {
++ status = "okay";
++};
++
++&m4_hash2 {
++ status = "okay";
++};
++
++&m4_i2c2 {
++ pinctrl-names = "rproc_default";
++ pinctrl-0 = <&i2c2_pins_a>;
++ status = "okay";
++};
++
++&m4_rng2 {
++ status = "okay";
++};
++
++&m4_rproc {
++ m4_system_resources {
++ status = "okay";
++
++ button {
++ compatible = "rproc-srm-dev";
++ interrupt-parent = <&gpioa>;
++ interrupts = <14 2>;
++ interrupt-names = "irq";
++ status = "okay";
++ };
++
++ m4_led: m4_led {
++ compatible = "rproc-srm-dev";
++ pinctrl-names = "rproc_default", "rproc_sleep";
++ pinctrl-0 = <&leds_orange_pins>;
++ pinctrl-1 = <&leds_orange_sleep_pins>;
++ status = "okay";
++ };
++ };
++};
++
++&m4_spi4 {
++ pinctrl-names = "rproc_default";
++ pinctrl-0 = <&spi4_pins_a>;
++ status = "okay";
++};
++
++
++&m4_timers2 {
++ pinctrl-names = "rproc_default";
++ status = "okay";
++};
++
++&m4_timers1 {
++ pinctrl-names = "rproc_default";
++ pinctrl-0 = <&timer1_pins>;
++ status = "okay";
++};
++
++&m4_uart7 {
++ pinctrl-names = "rproc_default";
++ pinctrl-0 = <&uart7_pins>;
++ status = "okay";
++};
++
++&pinctrl {
++ uart7_pins: uart7-test-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
++ bias-disable;
++ };
++ };
++
++ timer1_pins: pwm1-test-0 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */
++ bias-pull-down;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ };
++
++ leds_orange_pins: leds_orange_test-0 {
++ pins {
++ pinmux = <STM32_PINMUX('H', 7, GPIO)>;
++ bias-pull-up;
++ drive-push-pull;
++ output-low;
++ slew-rate = <0>;
++ };
++ };
++
++ leds_orange_sleep_pins: leds_orange_sleep_test-0 {
++ pins {
++ pinmux = <STM32_PINMUX('H', 7, ANALOG)>;
++ };
++ };
++};
++
++&timers1 {
++ status = "disabled";
++};
+diff --git a/arch/arm/dts/phycore-stm32mp1-1-u-boot.dtsi b/arch/arm/dts/phycore-stm32mp1-1-u-boot.dtsi
+new file mode 100644
+index 0000000..812d2ac
+--- /dev/null
++++ b/arch/arm/dts/phycore-stm32mp1-1-u-boot.dtsi
+@@ -0,0 +1,231 @@
++// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
++/*
++ * Copyright : STMicroelectronics 2018
++ */
++
++#include <dt-bindings/clock/stm32mp1-clksrc.h>
++#include "stm32mp157-u-boot.dtsi"
++#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
++
++/ {
++ aliases {
++ i2c3 = &i2c4;
++ mmc0 = &sdmmc1;
++ mmc1 = &sdmmc2;
++ spi0 = &qspi;
++ };
++
++ config {
++ u-boot,boot-led = "heartbeat";
++ st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
++ st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
++ };
++
++ led {
++ blue {
++ default-state = "on";
++ };
++ };
++};
++
++
++&flash0 {
++ compatible = "spi-flash";
++ u-boot,dm-spl;
++};
++
++&qspi {
++ u-boot,dm-spl;
++};
++
++&qspi_clk_pins_a {
++ u-boot,dm-spl;
++ pins {
++ u-boot,dm-spl;
++ };
++};
++
++&qspi_bk1_pins_a {
++ u-boot,dm-spl;
++ pins1 {
++ u-boot,dm-spl;
++ };
++ pins2 {
++ u-boot,dm-spl;
++ };
++};
++
++&clk_hse {
++ st,digbypass;
++};
++
++&i2c4 {
++ u-boot,dm-pre-reloc;
++};
++
++&i2c4_pins_a {
++ u-boot,dm-pre-reloc;
++ pins {
++ u-boot,dm-pre-reloc;
++ };
++};
++
++&pmic {
++ u-boot,dm-pre-reloc;
++};
++
++&ethernet0 {
++ u-boot,dm-pre-reloc;
++};
++
++&rcc {
++ st,clksrc = <
++ CLK_MPU_PLL1P
++ CLK_AXI_PLL2P
++ CLK_MCU_PLL3P
++ CLK_PLL12_HSE
++ CLK_PLL3_HSE
++ CLK_PLL4_HSE
++ CLK_RTC_LSE
++ CLK_MCO1_DISABLED
++ CLK_MCO2_DISABLED
++ >;
++
++ st,clkdiv = <
++ 1 /*MPU*/
++ 0 /*AXI*/
++ 0 /*MCU*/
++ 1 /*APB1*/
++ 1 /*APB2*/
++ 1 /*APB3*/
++ 1 /*APB4*/
++ 2 /*APB5*/
++ 23 /*RTC*/
++ 0 /*MCO1*/
++ 0 /*MCO2*/
++ >;
++
++ st,pkcs = <
++ CLK_CKPER_HSE
++ CLK_FMC_ACLK
++ CLK_QSPI_ACLK
++ CLK_ETH_PLL4P
++ CLK_SDMMC12_PLL4P
++ CLK_DSI_DSIPLL
++ CLK_STGEN_HSE
++ CLK_USBPHY_HSE
++ CLK_SPI2S1_PLL3Q
++ CLK_SPI2S23_PLL3Q
++ CLK_SPI45_HSI
++ CLK_SPI6_HSI
++ CLK_I2C46_HSI
++ CLK_SDMMC3_PLL4P
++ CLK_USBO_USBPHY
++ CLK_ADC_CKPER
++ CLK_CEC_LSE
++ CLK_I2C12_HSI
++ CLK_I2C35_HSI
++ CLK_UART1_HSI
++ CLK_UART24_HSI
++ CLK_UART35_HSI
++ CLK_UART6_HSI
++ CLK_UART78_HSI
++ CLK_SPDIF_PLL4P
++ CLK_FDCAN_PLL4Q
++ CLK_SAI1_PLL3Q
++ CLK_SAI2_PLL3Q
++ CLK_SAI3_PLL3Q
++ CLK_SAI4_PLL3Q
++ CLK_RNG1_LSI
++ CLK_RNG2_LSI
++ CLK_LPTIM1_PCLK1
++ CLK_LPTIM23_PCLK3
++ CLK_LPTIM45_LSE
++ >;
++
++ /* VCO = 1300.0 MHz => P = 650 (CPU) */
++ pll1: st,pll@0 {
++ cfg = < 2 80 0 0 0 PQR(1,0,0) >;
++ frac = < 0x800 >;
++ u-boot,dm-pre-reloc;
++ };
++
++ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
++ pll2: st,pll@1 {
++ cfg = < 2 65 1 0 0 PQR(1,1,1) >;
++ frac = < 0x1400 >;
++ u-boot,dm-pre-reloc;
++ };
++
++ /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
++ pll3: st,pll@2 {
++ cfg = < 1 33 1 16 36 PQR(1,1,1) >;
++ frac = < 0x1a04 >;
++ u-boot,dm-pre-reloc;
++ };
++
++ /* VCO = 750.0 MHz, P=125, Q=62.5, R=62.5 */
++ pll4: st,pll@3 {
++ cfg = <3 124 5 11 11 PQR(1,1,1)>;
++ u-boot,dm-pre-reloc;
++ };
++};
++
++&sdmmc1 {
++ u-boot,dm-spl;
++};
++
++&sdmmc1_b4_pins_a {
++ u-boot,dm-spl;
++ pins1 {
++ u-boot,dm-spl;
++ };
++ pins2 {
++ u-boot,dm-spl;
++ };
++};
++
++&sdmmc1_dir_pins_a {
++ u-boot,dm-spl;
++ pins1 {
++ u-boot,dm-spl;
++ };
++ pins2 {
++ u-boot,dm-spl;
++ };
++};
++
++&sdmmc2 {
++ u-boot,dm-spl;
++};
++
++&sdmmc2_b4_pins_a {
++ u-boot,dm-spl;
++ pins1 {
++ u-boot,dm-spl;
++ };
++ pins2 {
++ u-boot,dm-spl;
++ };
++};
++
++&sdmmc2_d47_pins_a {
++ u-boot,dm-spl;
++ pins {
++ u-boot,dm-spl;
++ };
++};
++
++&uart4 {
++ u-boot,dm-pre-reloc;
++};
++
++&uart4_pins_a {
++ u-boot,dm-pre-reloc;
++ pins1 {
++ u-boot,dm-pre-reloc;
++ };
++ pins2 {
++ u-boot,dm-pre-reloc;
++ };
++};
+diff --git a/arch/arm/dts/phycore-stm32mp1-1.dts b/arch/arm/dts/phycore-stm32mp1-1.dts
+new file mode 100644
+index 0000000..44d113a
+--- /dev/null
++++ b/arch/arm/dts/phycore-stm32mp1-1.dts
+@@ -0,0 +1,15 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++/dts-v1/;
++
++#include "phycore-stm32mp1-1.dtsi"
++
++/ {
++ model = "Phytec GmbH phycore-stm32mp1-1 Dev Board";
++ compatible = "phycore-stm32mp1-1", "phytec,pcm939-1517-1-002", "st,stm32mp157";
++
++};
+diff --git a/arch/arm/dts/phycore-stm32mp1-1.dtsi b/arch/arm/dts/phycore-stm32mp1-1.dtsi
+new file mode 100644
+index 0000000..ce72a4b
+--- /dev/null
++++ b/arch/arm/dts/phycore-stm32mp1-1.dtsi
+@@ -0,0 +1,427 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++/dts-v1/;
++
++#include "phycore-stm32mp157cac-som.dtsi"
++
++/ {
++ model = "Phytec GmbH phycore-stm32mp1-1 Dev Board";
++ compatible = "phytec,pcm939-1517-1-002", "st,stm32mp157";
++
++ aliases {
++ ethernet0 = &ethernet0;
++ rtc0 = &i2c4_rtc;
++ rtc1 = &rtc;
++ serial0 = &uart4;
++ serial1 = &uart7;
++ serial2 = &usart1;
++ serial3 = &usart3;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ tlv320_mclk: oscillator {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <19200000>;
++ clock-output-names = "tlv320-mclk";
++ };
++
++ sound {
++ compatible = "audio-graph-card";
++ label = "STM32MP1_PHYCORE";
++ dais = <&sai2b_port>;
++ status = "okay";
++ };
++
++ usb_phy_tuning: usb-phy-tuning {
++ st,hs-dc-level = <2>;
++ st,fs-rftime-tuning;
++ st,hs-rftime-reduction;
++ st,hs-current-trim = <15>;
++ st,hs-impedance-trim = <1>;
++ st,squelch-level = <3>;
++ st,hs-rx-offset = <2>;
++ st,no-lsfs-sc;
++ };
++};
++
++&adc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&adc12_usb_pwr_pins_a>;
++ vdd-supply = <&vdd>;
++ vdda-supply = <&vdd>;
++ vref-supply = <&vrefbuf>;
++ status = "disabled";
++ adc1: adc@0 {
++ /*
++ * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
++ * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
++ * 5 * (56 + 47kOhms) * 5pF => 2.5us.
++ * Use arbitrary margin here (e.g. 5µs).
++ */
++ st,min-sample-time-nsecs = <5000>;
++ /* ANA0, ANA1, USB Type-C CC1 & CC2 */
++ st,adc-channels = <0 1 18 19>;
++ status = "okay";
++ };
++ adc2: adc@100 {
++ /* ANA0, ANA1, temp sensor, USB Type-C CC1 & CC2 */
++ st,adc-channels = <0 1 12 18 19>;
++ /* temperature sensor min sample time */
++ st,min-sample-time-nsecs = <10000>;
++ status = "okay";
++ };
++ adc_temp: temp {
++ status = "okay";
++ };
++};
++
++&m_can1 {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&m_can1_pins_a>;
++ pinctrl-1 = <&m_can1_sleep_pins_a>;
++ status = "okay";
++};
++
++&ethernet0 {
++ status = "okay";
++ pinctrl-0 = <&ethernet0_rgmii_pins_a>;
++ pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
++ pinctrl-names = "default", "sleep";
++ phy-mode = "rgmii";
++ st,eth_clk_sel = <1>;
++ max-speed = <1000>;
++ phy-handle = <&phy0>;
++
++ mdio0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "snps,dwmac-mdio";
++
++ phy0: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <1>;
++ interrupt-parent = <&gpiog>;
++ interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
++ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
++ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
++ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
++ ti,min-output-impedance;
++ enet-phy-lane-no-swap;
++ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
++ };
++ };
++};
++
++&i2c1 {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&i2c1_pins_a>;
++ pinctrl-1 = <&i2c1_pins_sleep_a>;
++ i2c-scl-rising-time-ns = <185>;
++ i2c-scl-falling-time-ns = <20>;
++ status = "okay";
++ /delete-property/dmas;
++ /delete-property/dma-names;
++
++ codec: tlv320@18 {
++ compatible = "ti,tlv320aic3007";
++ #sound-dai-cells = <0>;
++ reg = <0x18>;
++ status = "okay";
++
++ ai3x-micbias-vg = <2>;
++
++ /* gpio-reset = <&gpio5 8 GPIO_ACTIVE_LOW>; */
++ AVDD-supply = <&v3v3>;
++ IOVDD-supply = <&v3v3>;
++ DRVDD-supply = <&v3v3>;
++ DVDD-supply = <&v1v8_audio>;
++
++ clocks = <&sai2b>;
++ clock-names = "MCLK";
++
++ tlv320_port: port {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ tlv320_tx_endpoint: endpoint@0 {
++ reg = <0>;
++ remote-endpoint = <&sai2b_endpoint>;
++ frame-master;
++ bitclock-master;
++ };
++
++ tlv320_rx_endpoint: endpoint@1 {
++ reg = <1>;
++ remote-endpoint = <&sai2a_endpoint>;
++ frame-master;
++ bitclock-master;
++ };
++ };
++ };
++
++ touchscreen@2a {
++ compatible = "focaltech,ft6236";
++ reg = <0x2a>;
++ interrupts = <8 2>;
++ interrupt-parent = <&gpioi>;
++ interrupt-controller;
++ touchscreen-size-x = <480>;
++ touchscreen-size-y = <800>;
++ status = "okay";
++ };
++
++ touchscreen@38 {
++ compatible = "focaltech,ft6336";
++ reg = <0x38>;
++ interrupts = <8 2>;
++ interrupt-parent = <&gpioi>;
++ interrupt-controller;
++ touchscreen-size-x = <480>;
++ touchscreen-size-y = <800>;
++ status = "okay";
++ };
++};
++
++&i2c2 {
++ status = "disabled";
++};
++
++&i2s2 {
++ clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
++ clock-names = "pclk", "i2sclk", "x8k", "x11k";
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&i2s2_pins_a>;
++ pinctrl-1 = <&i2s2_pins_sleep_a>;
++ status = "disabled";
++
++ i2s2_port: port {
++ };
++};
++
++&sai2 {
++ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
++ clock-names = "pclk", "x8k", "x11k";
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&sai2b_pins_b>;
++ pinctrl-1 = <&sai2b_sleep_pins_b>;
++ status = "okay";
++
++ sai2a: audio-controller@4400b004 {
++ dma-names = "rx";
++ st,sync = <&sai2b 2>;
++ status = "disabled";
++ clocks = <&rcc SAI2_K>, <&sai2b>;
++ clock-names = "sai_ck", "MCLK";
++
++ sai2a_port: port {
++ sai2a_endpoint: endpoint {
++ remote-endpoint = <&tlv320_rx_endpoint>;
++ format = "i2s";
++ mclk-fs = <256>;
++ dai-tdm-slot-num = <2>;
++ dai-tdm-slot-width = <32>;
++ };
++ };
++ };
++
++ sai2b: audio-controller@4400b024 {
++ #clock-cells = <0>;
++ dma-names = "tx";
++ clocks = <&rcc SAI2_K>;
++ clock-names = "sai_ck";
++ status = "okay";
++
++ sai2b_port: port {
++ sai2b_endpoint: endpoint {
++ remote-endpoint = <&tlv320_tx_endpoint>;
++ format = "i2s";
++ mclk-fs = <256>;
++ dai-tdm-slot-num = <2>;
++ dai-tdm-slot-width = <32>;
++ };
++ };
++ };
++
++
++};
++
++&sdmmc1 {
++ pinctrl-names = "default", "opendrain", "sleep";
++ pinctrl-0 = <&sdmmc1_b4_pins_a>;
++ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
++ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
++ broken-cd;
++ st,neg-edge;
++ bus-width = <4>;
++ max-frequency = <10000000>;
++ vmmc-supply = <&v3v3>;
++ status = "okay";
++};
++
++&spi4 {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&spi4_pins_a>;
++ pinctrl-1 = <&spi4_sleep_pins_a>;
++ status = "disabled";
++};
++
++&spi5 {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&spi5_pins_a>;
++ pinctrl-1 = <&spi5_sleep_pins_a>;
++ status = "disabled";
++};
++
++&timers1 {
++ /* spare dmas for other usage */
++ /delete-property/dmas;
++ /delete-property/dma-names;
++ pwm {
++ pinctrl-0 = <&pwm1_pins_a>;
++ pinctrl-1 = <&pwm1_sleep_pins_a>;
++ pinctrl-names = "default", "sleep";
++ status = "disabled";
++ };
++ timer@0 {
++ status = "okay";
++ };
++};
++
++&timers3 {
++ /delete-property/dmas;
++ /delete-property/dma-names;
++ pwm {
++ pinctrl-0 = <&pwm3_pins_a>;
++ pinctrl-1 = <&pwm3_sleep_pins_a>;
++ pinctrl-names = "default", "sleep";
++ status = "disabled";
++ };
++ timer@2 {
++ status = "okay";
++ };
++};
++
++&timers4 {
++ /delete-property/dmas;
++ /delete-property/dma-names;
++ pwm {
++ pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>;
++ pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>;
++ pinctrl-names = "default", "sleep";
++ status = "disabled";
++ };
++ timer@3 {
++ status = "okay";
++ };
++};
++
++&timers5 {
++ /delete-property/dmas;
++ /delete-property/dma-names;
++ pwm {
++ pinctrl-0 = <&pwm5_pins_a>;
++ pinctrl-1 = <&pwm5_sleep_pins_a>;
++ pinctrl-names = "default", "sleep";
++ status = "disabled";
++ };
++ timer@4 {
++ status = "okay";
++ };
++};
++
++&timers6 {
++ status = "okay";
++ /* spare dmas for other usage */
++ /delete-property/dmas;
++ /delete-property/dma-names;
++ timer@5 {
++ status = "okay";
++ };
++};
++
++&uart4 {
++ pinctrl-names = "default", "sleep", "idle", "no_console_suspend";
++ pinctrl-0 = <&uart4_pins_a>;
++ pinctrl-1 = <&uart4_sleep_pins_a>;
++ pinctrl-2 = <&uart4_idle_pins_a>;
++ pinctrl-3 = <&uart4_pins_a>;
++ status = "okay";
++};
++
++&uart7 {
++ pinctrl-names = "default", "sleep", "idle";
++ pinctrl-0 = <&uart7_pins_a>;
++ pinctrl-1 = <&uart7_sleep_pins_a>;
++ pinctrl-2 = <&uart7_idle_pins_a>;
++ status = "okay";
++};
++
++&usart1 {
++ pinctrl-names = "default", "sleep", "idle";
++ pinctrl-0 = <&usart1_pins_a>;
++ pinctrl-1 = <&usart1_sleep_pins_a>;
++ pinctrl-2 = <&usart1_idle_pins_a>;
++ status = "okay";
++};
++
++&usart3 {
++ pinctrl-names = "default", "sleep", "idle";
++ pinctrl-0 = <&usart3_pins_b>;
++ pinctrl-1 = <&usart3_sleep_pins_b>;
++ pinctrl-2 = <&usart3_idle_pins_b>;
++ status = "okay";
++};
++
++&usbh_ehci {
++ phys = <&usbphyc_port0>;
++ phy-names = "usb";
++ status = "okay";
++ vbus-supply = <&vbus_sw>;
++};
++
++&usbotg_hs {
++ force-b-session-valid;
++ phys = <&usbphyc_port1 0>;
++ phy-names = "usb2-phy";
++ vbus-supply = <&vbus_otg>;
++ status = "okay";
++};
++
++&usbphyc {
++ vdd3v3-supply = <&vdd_usb>;
++ status = "okay";
++};
++
++&usbphyc_port0 {
++ st,phy-tuning = <&usb_phy_tuning>;
++};
++
++&usbphyc_port1 {
++ st,phy-tuning = <&usb_phy_tuning>;
++};
++
++&vrefbuf {
++ regulator-min-microvolt = <2500000>;
++ regulator-max-microvolt = <2500000>;
++ vdda-supply = <&vdd>;
++ status = "disabled";
++};
++
++/* Select display interface by commenting/uncommenting the following lines */
++/*#include "phycore-stm32mp1-dsi-lcd-mb1407.dtsi"*/
++#include "phycore-stm32mp1-peb-av01-hdmi.dtsi"
++/*#include "phycore-stm32mp1-peb-av02-lcd.dtsi"*/
++
++
++/* Selected connectors used commenting/uncommenting the following line */
++/*#include "phycore-stm32mp1-pi-hat-extension.dtsi"*/
++/*#include "phycore-stm32mp1-uno-r3-extension.dtsi"*/
++/*#include "phycore-stm32mp1-motor-control.dtsi"*/
+diff --git a/arch/arm/dts/phycore-stm32mp1-dsi-lcd-mb1407.dtsi b/arch/arm/dts/phycore-stm32mp1-dsi-lcd-mb1407.dtsi
+new file mode 100644
+index 0000000..64065b6
+--- /dev/null
++++ b/arch/arm/dts/phycore-stm32mp1-dsi-lcd-mb1407.dtsi
+@@ -0,0 +1,58 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++&ltdc {
++ dma-ranges;
++ status = "okay";
++
++ port {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ltdc_ep1_out: endpoint@1 {
++ reg = <1>;
++ remote-endpoint = <&dsi_in>;
++ };
++ };
++};
++
++&dsi {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ dsi_in: endpoint {
++ remote-endpoint = <&ltdc_ep1_out>;
++ };
++ };
++
++ port@1 {
++ reg = <1>;
++ dsi_out: endpoint {
++ remote-endpoint = <&panel_in>;
++ };
++ };
++ };
++
++ dsi_panel:panel@0 {
++ compatible = "orisetech,otm8009a";
++ reg = <0>;
++ reset-gpios = <&gpiod 9 GPIO_ACTIVE_LOW>;
++ status = "okay";
++
++ port {
++ panel_in: endpoint {
++ remote-endpoint = <&dsi_out>;
++ };
++ };
++ };
++};
+diff --git a/arch/arm/dts/phycore-stm32mp1-motor-control.dtsi b/arch/arm/dts/phycore-stm32mp1-motor-control.dtsi
+new file mode 100644
+index 0000000..cf2c3d1
+--- /dev/null
++++ b/arch/arm/dts/phycore-stm32mp1-motor-control.dtsi
+@@ -0,0 +1,6 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
+diff --git a/arch/arm/dts/phycore-stm32mp1-peb-av01-hdmi.dtsi b/arch/arm/dts/phycore-stm32mp1-peb-av01-hdmi.dtsi
+new file mode 100644
+index 0000000..391d343
+--- /dev/null
++++ b/arch/arm/dts/phycore-stm32mp1-peb-av01-hdmi.dtsi
+@@ -0,0 +1,43 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++&i2c1 {
++ tda19988@70 {
++ compatible = "nxp,tda998x";
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&ltdc_pins_a>;
++ pinctrl-1 = <&ltdc_pins_sleep_a>;
++ reg = <0x70>;
++ status = "okay";
++
++ ports {
++ port@0 {
++ hdmi_in: endpoint@0 {
++ remote-endpoint = <&ltdc_ep0_out>;
++ };
++ };
++ };
++ };
++};
++
++&ltdc {
++ dma-ranges;
++ status = "okay";
++
++ port {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ltdc_ep0_out: endpoint@0 {
++ reg = <0>;
++ remote-endpoint = <&hdmi_in>;
++ };
++ };
++};
++
++&dsi {
++ status = "disabled";
++};
+diff --git a/arch/arm/dts/phycore-stm32mp1-peb-av02-lcd.dtsi b/arch/arm/dts/phycore-stm32mp1-peb-av02-lcd.dtsi
+new file mode 100644
+index 0000000..56b9f9a
+--- /dev/null
++++ b/arch/arm/dts/phycore-stm32mp1-peb-av02-lcd.dtsi
+@@ -0,0 +1,96 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++/ {
++ panel_rgb: panel {
++ compatible = "edt,etm0700g0edh6";
++
++ status = "okay";
++ backlight = <&panel_backlight>;
++ enable-gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>;
++
++ port {
++ panel_in_rgb: endpoint {
++ remote-endpoint = <&ltdc_ep0_out>;
++ };
++ };
++ };
++
++ panel_backlight: panel-backlight {
++ compatible = "pwm-backlight";
++ pwms = <&pwm_5 0 100000 0>;
++ power-supply = <&v3v3>;
++
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <6>;
++ status = "okay";
++ };
++};
++
++&timers5 {
++ status = "okay";
++ /delete-property/dmas;
++ /delete-property/dma-names;
++ pwm_5: pwm {
++ #pwm-cells = <2>;
++ pinctrl-0 = <&pwm5_pins_a>;
++ pinctrl-1 = <&pwm5_sleep_pins_a>;
++ pinctrl-names = "default", "sleep";
++ status = "okay";
++ };
++
++ timer@4 {
++ status = "disabled";
++ };
++};
++
++&ltdc {
++ dma-ranges;
++ status = "okay";
++
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&ltdc_pins_a>;
++ pinctrl-1 = <&ltdc_pins_sleep_a>;
++
++ port {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ltdc_ep0_out: endpoint@0 {
++ reg = <0>;
++ remote-endpoint = <&panel_in_rgb>;
++ };
++ };
++};
++
++&i2c1 {
++ stmpe: touchctrl@44 {
++ compatible = "st,stmpe811";
++ reg = <0x44>;
++ interrupts = <3 2>;
++ interrupt-parent = <&gpioi>;
++ interrupt-controller;
++ status = "okay";
++
++ stmpe_touchscreen {
++ compatible = "st,stmpe-ts";
++ st,sample-time = <4>;
++ st,mod-12b = <1>;
++ st,ref-sel = <0>;
++ st,adc-freq = <1>;
++ st,ave-ctrl = <1>;
++ st,touch-det-delay = <2>;
++ st,settling = <2>;
++ st,fraction-z = <7>;
++ st,i-drive = <1>;
++ };
++ };
++};
++
++
++&dsi {
++ status = "disabled";
++};
+diff --git a/arch/arm/dts/phycore-stm32mp1-pi-hat-extension.dtsi b/arch/arm/dts/phycore-stm32mp1-pi-hat-extension.dtsi
+new file mode 100644
+index 0000000..cf2c3d1
+--- /dev/null
++++ b/arch/arm/dts/phycore-stm32mp1-pi-hat-extension.dtsi
+@@ -0,0 +1,6 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
+diff --git a/arch/arm/dts/phycore-stm32mp1-uno-r3-extension.dtsi b/arch/arm/dts/phycore-stm32mp1-uno-r3-extension.dtsi
+new file mode 100644
+index 0000000..cf2c3d1
+--- /dev/null
++++ b/arch/arm/dts/phycore-stm32mp1-uno-r3-extension.dtsi
+@@ -0,0 +1,6 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
+diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi
+index 183d7ba..b5bb5b2 100644
+--- a/arch/arm/dts/stm32mp157-pinctrl.dtsi
++++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi
+@@ -1121,7 +1121,7 @@
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
++ <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <1>;
+@@ -1140,7 +1140,7 @@
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
++ <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+@@ -1164,7 +1164,7 @@
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+- <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
++ <STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+@@ -1253,7 +1253,7 @@
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+- <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
++ <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
+@@ -1265,7 +1265,7 @@
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
+- <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
++ <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
+ };
+ };
+@@ -1385,7 +1385,7 @@
+
+ uart4_pins_a: uart4-0 {
+ pins1 {
+- pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
++ pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
+index 4de499e..54bc05e 100644
+--- a/arch/arm/dts/stm32mp157c.dtsi
++++ b/arch/arm/dts/stm32mp157c.dtsi
+@@ -58,6 +58,7 @@
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&intc>;
++ always-on;
+ };
+
+ clocks {
+@@ -430,8 +431,8 @@
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI2_K>;
+ resets = <&rcc SPI2_R>;
+- dmas = <&dmamux1 39 0x400 0x05>,
+- <&dmamux1 40 0x400 0x05>;
++ dmas = <&dmamux1 39 0x400 0x01>,
++ <&dmamux1 40 0x400 0x01>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
+ status = "disabled";
+@@ -456,8 +457,8 @@
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI3_K>;
+ resets = <&rcc SPI3_R>;
+- dmas = <&dmamux1 61 0x400 0x05>,
+- <&dmamux1 62 0x400 0x05>;
++ dmas = <&dmamux1 61 0x400 0x01>,
++ <&dmamux1 62 0x400 0x01>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
+ status = "disabled";
+@@ -756,8 +757,8 @@
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI1_K>;
+ resets = <&rcc SPI1_R>;
+- dmas = <&dmamux1 37 0x400 0x05>,
+- <&dmamux1 38 0x400 0x05>;
++ dmas = <&dmamux1 37 0x400 0x01>,
++ <&dmamux1 38 0x400 0x01>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
+ status = "disabled";
+@@ -782,8 +783,8 @@
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI4_K>;
+ resets = <&rcc SPI4_R>;
+- dmas = <&dmamux1 83 0x400 0x05>,
+- <&dmamux1 84 0x400 0x05>;
++ dmas = <&dmamux1 83 0x400 0x01>,
++ <&dmamux1 84 0x400 0x01>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
+ status = "disabled";
+@@ -870,8 +871,8 @@
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI5_K>;
+ resets = <&rcc SPI5_R>;
+- dmas = <&dmamux1 85 0x400 0x05>,
+- <&dmamux1 86 0x400 0x05>;
++ dmas = <&dmamux1 85 0x400 0x01>,
++ <&dmamux1 86 0x400 0x01>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd_core>;
+ status = "disabled";
+@@ -892,6 +893,8 @@
+
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x4 0x1c>;
++ clocks = <&rcc SAI1_K>;
++ clock-names = "sai_ck";
+ dmas = <&dmamux1 87 0x400 0x01>;
+ status = "disabled";
+ };
+@@ -900,6 +903,8 @@
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x1c>;
++ clocks = <&rcc SAI1_K>;
++ clock-names = "sai_ck";
+ dmas = <&dmamux1 88 0x400 0x01>;
+ status = "disabled";
+ };
+@@ -919,6 +924,8 @@
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x4 0x1c>;
++ clocks = <&rcc SAI2_K>;
++ clock-names = "sai_ck";
+ dmas = <&dmamux1 89 0x400 0x01>;
+ status = "disabled";
+ };
+@@ -927,6 +934,8 @@
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x1c>;
++ clocks = <&rcc SAI2_K>;
++ clock-names = "sai_ck";
+ dmas = <&dmamux1 90 0x400 0x01>;
+ status = "disabled";
+ };
+@@ -946,6 +955,8 @@
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x04 0x1c>;
++ clocks = <&rcc SAI3_K>;
++ clock-names = "sai_ck";
+ dmas = <&dmamux1 113 0x400 0x01>;
+ status = "disabled";
+ };
+@@ -954,6 +965,8 @@
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x1c>;
++ clocks = <&rcc SAI3_K>;
++ clock-names = "sai_ck";
+ dmas = <&dmamux1 114 0x400 0x01>;
+ status = "disabled";
+ };
+@@ -1221,7 +1234,6 @@
+ g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
+ dr_mode = "otg";
+ usb33d-supply = <&usb33>;
+- power-domains = <&pd_core>;
+ status = "disabled";
+ };
+
+@@ -1442,6 +1454,8 @@
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x1c>;
++ clocks = <&rcc SAI4_K>;
++ clock-names = "sai_ck";
+ dmas = <&dmamux1 100 0x400 0x01>;
+ status = "disabled";
+ };
+@@ -1735,10 +1749,14 @@
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
++ "eth-ck",
++ "syscfg-clk",
+ "ethstp";
+ clocks = <&rcc ETHMAC>,
+ <&rcc ETHTX>,
+ <&rcc ETHRX>,
++ <&rcc ETHCK_K>,
++ <&rcc SYSCFG>,
+ <&rcc ETHSTP>;
+ st,syscon = <&syscfg 0x4>;
+ snps,mixed-burst;
+@@ -1756,7 +1774,6 @@
+ clocks = <&rcc USBH>;
+ resets = <&rcc USBH_R>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+- power-domains = <&pd_core>;
+ status = "disabled";
+ };
+
+@@ -1767,7 +1784,6 @@
+ resets = <&rcc USBH_R>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ companion = <&usbh_ohci>;
+- power-domains = <&pd_core>;
+ status = "disabled";
+ };
+
+diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
+index 5d5ce4a..8d8ade3 100644
+--- a/arch/arm/mach-stm32mp/cpu.c
++++ b/arch/arm/mach-stm32mp/cpu.c
+@@ -22,6 +22,7 @@
+ #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
+ #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
+ #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
++#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
+
+ #define RCC_BDCR_VSWRST BIT(31)
+ #define RCC_BDCR_RTCSRC GENMASK(17, 16)
+@@ -49,6 +50,9 @@
+ #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
+ #define DBGMCU_IDC_REV_ID_SHIFT 16
+
++/* GPIOZ registers */
++#define GPIOZ_SECCFGR 0x54004030
++
+ /* boot interface from Bootrom
+ * - boot instance = bit 31:16
+ * - boot device = bit 15:0
+@@ -142,6 +146,10 @@ static void security_init(void)
+ * Bit 16 ITAMP1E: RTC power domain supply monitoring
+ */
+ writel(0x0, TAMP_CR1);
++
++ /* GPIOZ: deactivate the security */
++ writel(BIT(0), RCC_MP_AHB5ENSETR);
++ writel(0x0, GPIOZ_SECCFGR);
+ }
+ #endif /* CONFIG_STM32MP1_TRUSTED */
+
+@@ -399,14 +407,16 @@ static void setup_boot_mode(void)
+ env_set("boot_instance", cmd);
+ break;
+ case BOOT_FLASH_NAND:
+- sprintf(cmd, "%d", instance);
+ env_set("boot_device", "nand");
+- env_set("boot_instance", cmd);
++ env_set("boot_instance", "0");
+ break;
+ case BOOT_FLASH_NOR:
+ env_set("boot_device", "nor");
+ env_set("boot_instance", "0");
+ break;
++ default:
++ pr_debug("unexpected boot mode = %x\n", boot_mode);
++ break;
+ }
+
+ switch (forced_mode) {
+@@ -415,8 +425,8 @@ static void setup_boot_mode(void)
+ env_set("preboot", "env set preboot; fastboot 0");
+ break;
+ case BOOT_STM32PROG:
+- printf("Enter STM32CubeProgrammer mode!\n");
+- env_set("preboot", "env set preboot; stm32prog usb 0");
++ env_set("boot_device", "usb");
++ env_set("boot_instance", "0");
+ break;
+ case BOOT_UMS_MMC0:
+ case BOOT_UMS_MMC1:
+@@ -430,8 +440,9 @@ static void setup_boot_mode(void)
+ env_set("preboot", "env set preboot; run altbootcmd");
+ break;
+ case BOOT_NORMAL:
++ break;
+ default:
+- pr_debug("unexpected boot mode = %x\n", boot_mode);
++ pr_debug("unexpected forced boot mode = %x\n", forced_mode);
+ break;
+ }
+
+diff --git a/board/st/stm32mp1/extlinux.conf b/board/st/stm32mp1/extlinux.conf
+index 2b46328..3a03866 100644
+--- a/board/st/stm32mp1/extlinux.conf
++++ b/board/st/stm32mp1/extlinux.conf
+@@ -18,3 +18,11 @@ LABEL stm32mp157c-dk2
+ LABEL stm32mp157c-dk2-m4
+ KERNEL /fit_copro_kernel_dtb.itb#dk2-m4
+ APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200
++
++LABEL phycore-stm32mp1-1
++ KERNEL /fit_kernel_dtb.itb#phycore
++ APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200
++
++LABEL phycore-stm32mp1-1-m4
++ KERNEL /fit_kernel_dtb.itb#phycore-m4
++ APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200
+diff --git a/board/st/stm32mp1/fit_copro_kernel_dtb.its b/board/st/stm32mp1/fit_copro_kernel_dtb.its
+index 7582fc3..0910585 100644
+--- a/board/st/stm32mp1/fit_copro_kernel_dtb.its
++++ b/board/st/stm32mp1/fit_copro_kernel_dtb.its
+@@ -57,6 +57,17 @@
+ algo = "sha1";
+ };
+ };
++
++ fdt-phycore {
++ description = "FDT phycore";
++ data = /incbin/("phycore-stm32mp1-1.dtb");
++ type = "flat_dt";
++ arch = "arm";
++ compression = "none";
++ hash-1 {
++ algo = "sha1";
++ };
++ };
+ };
+
+ configurations {
+@@ -99,5 +110,25 @@
+ algo = "sha1";
+ };
+ };
++
++ phycore-m4 {
++ description = "phycore-m4";
++ loadables = "copro";
++ kernel = "kernel";
++ fdt = "fdt-phycore";
++ hash-1 {
++ algo = "sha1";
++ };
++ };
++
++ phycore {
++ description = "phycore";
++ kernel = "kernel";
++ fdt = "fdt-phycore";
++ hash-1 {
++ algo = "sha1";
++ };
++ };
++
+ };
+ };
+diff --git a/board/st/stm32mp1/fit_kernel_dtb.its b/board/st/stm32mp1/fit_kernel_dtb.its
+index 18d03eb..176fce5 100644
+--- a/board/st/stm32mp1/fit_kernel_dtb.its
++++ b/board/st/stm32mp1/fit_kernel_dtb.its
+@@ -56,6 +56,19 @@
+ algo = "sha1";
+ };
+ };
++
++ fdt-phycore {
++ description = "FDT phyCORE";
++ data = /incbin/("phycore-stm32mp1-1.dtb");
++ type = "flat_dt";
++ arch = "arm";
++ compression = "none";
++ hash-1 {
++ algo = "sha1";
++ };
++ };
++
++
+ };
+
+ configurations {
+@@ -78,5 +91,16 @@
+ algo = "sha1";
+ };
+ };
++
++ phycore {
++ description = "phycore";
++ kernel = "kernel";
++ fdt = "fdt-phycore";
++ hash-1 {
++ algo = "sha1";
++ };
++ };
++
++
+ };
+ };
+diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
+index ad3424e..671aa76 100644
+--- a/configs/stm32mp15_basic_defconfig
++++ b/configs/stm32mp15_basic_defconfig
+@@ -72,13 +72,15 @@ CONFIG_SPI_FLASH_MACRONIX=y
+ CONFIG_SPI_FLASH_SPANSION=y
+ CONFIG_SPI_FLASH_STMICRO=y
+ CONFIG_SPI_FLASH_WINBOND=y
+-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_SPI_FLASH_USE_4K_SECTORS=y
+ CONFIG_SPI_FLASH_MTD=y
+-CONFIG_PHY_FIXED=y
+ CONFIG_DM_ETH=y
+ CONFIG_DWC_ETH_QOS=y
+ CONFIG_PHY=y
+ CONFIG_PHY_STM32_USBPHYC=y
++CONFIG_PHY_TI=y
++CONFIG_PHY_ADDR_ENABLE=y
++CONFIG_PHY_ADDR=1
+ CONFIG_PINCONF=y
+ # CONFIG_SPL_PINCTRL_FULL is not set
+ CONFIG_PINCTRL_STMFX=y
+@@ -116,3 +118,8 @@ CONFIG_VIDEO_STM32_MAX_YRES=800
+ CONFIG_STM32MP_WATCHDOG=y
+ CONFIG_FDT_FIXUP_PARTITIONS=y
+ # CONFIG_EFI_LOADER is not set
++#CONFIG_MTD_NOR_FLASH is not set
++CONFIG_STM32_FLASH=y
++CONFIG_SPI_FLASH_SUPPORT=y
++CONFIG_SPI_FLASH_DATAFLASH=y
++CONFIG_MTD_PARTITIONS=y
+diff --git a/configs/stm32mp15_optee_defconfig b/configs/stm32mp15_optee_defconfig
+index a24727c..382d785 100644
+--- a/configs/stm32mp15_optee_defconfig
++++ b/configs/stm32mp15_optee_defconfig
+@@ -69,6 +69,7 @@ CONFIG_DM_ETH=y
+ CONFIG_DWC_ETH_QOS=y
+ CONFIG_PHY=y
+ CONFIG_PHY_STM32_USBPHYC=y
++CONFIG_PHY_TI=y
+ CONFIG_PINCONF=y
+ CONFIG_PINCTRL_STMFX=y
+ CONFIG_DM_PMIC=y
+diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
+index e41506b..ca2c59e 100644
+--- a/configs/stm32mp15_trusted_defconfig
++++ b/configs/stm32mp15_trusted_defconfig
+@@ -61,13 +61,16 @@ CONFIG_SPI_FLASH_MACRONIX=y
+ CONFIG_SPI_FLASH_SPANSION=y
+ CONFIG_SPI_FLASH_STMICRO=y
+ CONFIG_SPI_FLASH_WINBOND=y
+-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_SPI_FLASH_USE_4K_SECTORS=y
+ CONFIG_SPI_FLASH_MTD=y
+-CONFIG_PHY_FIXED=y
+ CONFIG_DM_ETH=y
+ CONFIG_DWC_ETH_QOS=y
++CONFIG_NET_RANDOM_ETHADDR=y
+ CONFIG_PHY=y
+ CONFIG_PHY_STM32_USBPHYC=y
++CONFIG_PHY_TI=y
++#CONFIG_PHY_ADDR_ENABLE is not set
++CONFIG_PHY_ADDR=1
+ CONFIG_PINCONF=y
+ CONFIG_PINCTRL_STMFX=y
+ CONFIG_DM_PMIC=y
+@@ -102,3 +105,8 @@ CONFIG_VIDEO_STM32_MAX_YRES=800
+ CONFIG_STM32MP_WATCHDOG=y
+ CONFIG_FDT_FIXUP_PARTITIONS=y
+ # CONFIG_EFI_LOADER is not set
++# CONFIG_MTD_NOR_FLASH is not set
++CONFIG_STM32_FLASH=y
++CONFIG_SPI_FLASH_SUPPORT=y
++CONFIG_SPI_FLASH_DATAFLASH=y
++CONFIG_MTD_PARTITIONS=y
+diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
+index 79f834b..9659550 100644
+--- a/drivers/clk/clk_stm32mp1.c
++++ b/drivers/clk/clk_stm32mp1.c
+@@ -171,6 +171,7 @@ DECLARE_GLOBAL_DATA_PTR;
+ /* used for ALL PLLNCR registers */
+ #define RCC_PLLNCR_PLLON BIT(0)
+ #define RCC_PLLNCR_PLLRDY BIT(1)
++#define RCC_PLLNCR_SSCG_CTRL BIT(2)
+ #define RCC_PLLNCR_DIVPEN BIT(4)
+ #define RCC_PLLNCR_DIVQEN BIT(5)
+ #define RCC_PLLNCR_DIVREN BIT(6)
+@@ -574,7 +575,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
+
+ STM32MP1_CLK_SEC_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
+
+- STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _ETH_SEL),
++ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
+@@ -625,13 +626,13 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
+ STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
+ sdmmc3_parents),
+ STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
+- STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
+- STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
++ STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents),
++ STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents),
+ STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
+ STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
+ STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
+ STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
+- STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
++ STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents),
+ };
+
+ #ifdef STM32MP1_CLOCK_TREE_INIT
+@@ -1340,7 +1341,10 @@ static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
+ {
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+
+- writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
++ clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
++ RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
++ RCC_PLLNCR_DIVREN,
++ RCC_PLLNCR_PLLON);
+ }
+
+ static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
+@@ -1459,6 +1463,8 @@ static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
+ RCC_PLLNCSGR_SSCG_MODE_MASK);
+
+ writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
++
++ setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
+ }
+
+ static __maybe_unused int pll_set_rate(struct udevice *dev,
+diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
+index 2cb35f3..5609b69 100644
+--- a/drivers/firmware/psci.c
++++ b/drivers/firmware/psci.c
+@@ -15,7 +15,7 @@
+ #include <linux/printk.h>
+ #include <linux/psci.h>
+
+-psci_fn *invoke_psci_fn;
++psci_fn *invoke_psci_fn __attribute__((section(".data")));
+
+ static unsigned long __invoke_psci_fn_hvc(unsigned long function_id,
+ unsigned long arg0, unsigned long arg1,
+diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
+index 072b8c8..d93b026 100644
+--- a/drivers/net/dwc_eth_qos.c
++++ b/drivers/net/dwc_eth_qos.c
+@@ -905,14 +905,17 @@ static int eqos_adjust_link(struct udevice *dev)
+ case SPEED_1000:
+ en_calibration = true;
+ ret = eqos_set_gmii_speed(dev);
++ pr_err("eqos_adjust_link SPEED_1000 \n");
+ break;
+ case SPEED_100:
+ en_calibration = true;
+ ret = eqos_set_mii_speed_100(dev);
++ pr_err("eqos_adjust_link SPEED_100 \n");
+ break;
+ case SPEED_10:
+ en_calibration = false;
+ ret = eqos_set_mii_speed_10(dev);
++ pr_err("eqos_adjust_link SPEED_10 \n");
+ break;
+ default:
+ pr_err("invalid speed %d", eqos->phy->speed);
+@@ -994,7 +997,9 @@ static int eqos_write_hwaddr(struct udevice *dev)
+ static int eqos_start(struct udevice *dev)
+ {
+ struct eqos_priv *eqos = dev_get_priv(dev);
++ struct ofnode_phandle_args phandle_args;
+ int ret, i;
++ int addr =-1;
+ ulong rate;
+ u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
+ ulong last_rx_desc;
+@@ -1004,10 +1009,16 @@ static int eqos_start(struct udevice *dev)
+ eqos->tx_desc_idx = 0;
+ eqos->rx_desc_idx = 0;
+
++ ret = eqos->config->ops->eqos_start_clks(dev);
++ if (ret < 0) {
++ pr_err("eqos_start_clks() failed: %d", ret);
++ goto err;
++ }
++
+ ret = eqos->config->ops->eqos_start_resets(dev);
+ if (ret < 0) {
+ pr_err("eqos_start_resets() failed: %d", ret);
+- goto err;
++ goto err_stop_clks;
+ }
+
+ udelay(10);
+@@ -1031,6 +1042,39 @@ static int eqos_start(struct udevice *dev)
+ val = (rate / 1000000) - 1;
+ writel(val, &eqos->mac_regs->us_tic_counter);
+
++ /*
++ * if PHY was already connected and configured,
++ * don't need to reconnect/reconfigure again
++ */
++ if (!eqos->phy) {
++#ifdef CONFIG_PHY_ADDR_ENABLE
++ addr = CONFIG_PHY_ADDR;
++#else
++ if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
++ &phandle_args)) {
++ debug("phy-handle does exist %s\n", dev->name);
++ addr = ofnode_read_u32_default(phandle_args.node,
++ "reg", -1);
++ }
++#endif
++ if (addr == -1) {
++ pr_err("phyconnect() failed: No PHY address set !");
++ goto err_stop_resets;
++ }
++
++ eqos->phy = phy_connect(eqos->mii, addr, dev,
++ eqos->config->interface(dev));
++ if (!eqos->phy) {
++ pr_err("phy_connect() failed");
++ goto err_stop_resets;
++ }
++ ret = phy_config(eqos->phy);
++ if (ret < 0) {
++ pr_err("phy_config() failed: %d", ret);
++ goto err_shutdown_phy;
++ }
++ }
++
+ ret = phy_startup(eqos->phy);
+ if (ret < 0) {
+ pr_err("phy_startup() failed: %d", ret);
+@@ -1255,9 +1299,10 @@ static int eqos_start(struct udevice *dev)
+
+ err_shutdown_phy:
+ phy_shutdown(eqos->phy);
+- eqos->phy = NULL;
+ err_stop_resets:
+ eqos->config->ops->eqos_stop_resets(dev);
++err_stop_clks:
++ eqos->config->ops->eqos_stop_clks(dev);
+ err:
+ pr_err("FAILED: %d", ret);
+ return ret;
+@@ -1308,7 +1353,11 @@ void eqos_stop(struct udevice *dev)
+ clrbits_le32(&eqos->dma_regs->ch0_rx_control,
+ EQOS_DMA_CH0_RX_CONTROL_SR);
+
++ if (eqos->phy) {
++ phy_shutdown(eqos->phy);
++ }
+ eqos->config->ops->eqos_stop_resets(dev);
++ eqos->config->ops->eqos_stop_clks(dev);
+
+ debug("%s: OK\n", __func__);
+ }
+@@ -1679,8 +1728,8 @@ static int eqos_remove_resources_stm32(struct udevice *dev)
+ clk_free(&eqos->clk_tx);
+ clk_free(&eqos->clk_rx);
+ clk_free(&eqos->clk_master_bus);
+- if (clk_valid(&eqos->clk_ck))
+- clk_free(&eqos->clk_ck);
++ if (clk_valid(&eqos->clk_ck))
++ clk_free(&eqos->clk_ck);
+
+ debug("%s: OK\n", __func__);
+ return 0;
+@@ -1689,7 +1738,9 @@ static int eqos_remove_resources_stm32(struct udevice *dev)
+ static int eqos_probe(struct udevice *dev)
+ {
+ struct eqos_priv *eqos = dev_get_priv(dev);
++ struct ofnode_phandle_args phandle_args;
+ int ret;
++ int addr = -1;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+@@ -1721,6 +1772,7 @@ static int eqos_probe(struct udevice *dev)
+ eqos->mii = mdio_alloc();
+ if (!eqos->mii) {
+ pr_err("mdio_alloc() failed");
++ ret = -ENOMEM;
+ goto err_remove_resources_tegra;
+ }
+ eqos->mii->read = eqos_mdio_read;
+@@ -1734,17 +1786,26 @@ static int eqos_probe(struct udevice *dev)
+ goto err_free_mdio;
+ }
+
+- // Bring up PHY
+- ret = eqos->config->ops->eqos_start_clks(dev);
+- if (ret < 0) {
+- pr_err("eqos_start_clks() failed: %d", ret);
+- goto err_free_mdio;
+- }
++/*
++#ifdef CONFIG_PHY_ADDR_ENABLE
++ addr = CONFIG_PHY_ADDR;
++#else
++ if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
++ &phandle_args)) {
++ debug("phy-handle does exist %s\n", dev->name);
++ addr = ofnode_read_u32_default(phandle_args.node,
++ "reg", -1);
++ }
++#endif
++ if (addr == -1) {
++ pr_err("phyconnect() failed: No PHY address set !");
++ goto err_stop_resets;
++ }
+
+- eqos->phy = phy_connect(eqos->mii, 0, dev,
++ eqos->phy = phy_connect(eqos->mii, addr, dev,
+ eqos->config->interface(dev));
+ if (!eqos->phy) {
+- pr_err("phy_connect() failed");
++ pr_err("phy_connect() for address %d failed", addr);
+ goto err_stop_resets;
+ }
+ ret = phy_config(eqos->phy);
+@@ -1753,15 +1814,10 @@ static int eqos_probe(struct udevice *dev)
+ goto err_shutdown_phy;
+ }
+
++*/
+ debug("%s: OK\n", __func__);
+ return 0;
+
+-err_shutdown_phy:
+- phy_shutdown(eqos->phy);
+- eqos->phy = NULL;
+-err_stop_resets:
+- eqos->config->ops->eqos_stop_resets(dev);
+- eqos->config->ops->eqos_stop_clks(dev);
+ err_free_mdio:
+ mdio_free(eqos->mii);
+ err_remove_resources_tegra:
+@@ -1781,14 +1837,6 @@ static int eqos_remove(struct udevice *dev)
+
+ mdio_unregister(eqos->mii);
+ mdio_free(eqos->mii);
+-
+- if (eqos->phy) {
+- phy_shutdown(eqos->phy);
+- eqos->phy = NULL;
+- }
+-
+- eqos->config->ops->eqos_stop_resets(dev);
+- eqos->config->ops->eqos_stop_clks(dev);
+ eqos->config->ops->eqos_remove_resources(dev);
+
+ eqos_probe_resources_core(dev);
+diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
+index e837eb7..9fc4a76 100644
+--- a/drivers/net/phy/phy.c
++++ b/drivers/net/phy/phy.c
+@@ -907,7 +907,7 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr,
+ if (phydev)
+ phy_connect_dev(phydev, dev);
+ else
+- printf("Could not get PHY for %s: addr %d\n", bus->name, addr);
++ printf("Could not get PHY for %s: addr %d, interface %s\n", bus->name, addr, phy_string_for_interface(interface));
+ return phydev;
+ }
+
+diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
+index 6db6edd..628c8a8 100644
+--- a/drivers/net/phy/ti.c
++++ b/drivers/net/phy/ti.c
+@@ -1,16 +1,19 @@
+-// SPDX-License-Identifier: GPL-2.0
+ /*
+ * TI PHY drivers
+ *
++ * SPDX-License-Identifier: GPL-2.0
++ *
+ */
+ #include <common.h>
+ #include <phy.h>
+ #include <linux/compat.h>
+ #include <malloc.h>
+
++#include <fdtdec.h>
+ #include <dm.h>
+ #include <dt-bindings/net/ti-dp83867.h>
+
++DECLARE_GLOBAL_DATA_PTR;
+
+ /* TI DP83867 */
+ #define DP83867_DEVADDR 0x1f
+@@ -31,6 +34,9 @@
+ #define DP83867_SW_RESET BIT(15)
+ #define DP83867_SW_RESTART BIT(14)
+
++/* PHYCTRL bits */
++#define MII_DP83867_PHYCTRL_FORCE_LINK_GOOD BIT(10)
++
+ /* MICR Interrupt bits */
+ #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
+ #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
+@@ -54,6 +60,7 @@
+
+ /* PHY CTRL bits */
+ #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
++#define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14)
+ #define DP83867_PHYCR_RESERVED_MASK BIT(11)
+ #define DP83867_MDI_CROSSOVER 5
+ #define DP83867_MDI_CROSSOVER_AUTO 2
+@@ -93,9 +100,9 @@
+
+ #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
+ #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
++#define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
++#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
+ #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
+-#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK \
+- GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
+
+ /* CFG4 bits */
+ #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
+@@ -111,8 +118,8 @@ struct dp83867_private {
+ int tx_id_delay;
+ int fifo_depth;
+ int io_impedance;
+- bool rxctrl_strap_quirk;
+ int port_mirroring;
++ bool rxctrl_strap_quirk;
+ int clk_output_sel;
+ };
+
+@@ -189,7 +196,7 @@ static int dp83867_config_port_mirroring(struct phy_device *phydev)
+ u16 val;
+
+ val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
+- phydev->addr);
++ phydev->addr);
+
+ if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
+ val |= DP83867_CFG4_PORT_MIRROR_EN;
+@@ -197,7 +204,7 @@ static int dp83867_config_port_mirroring(struct phy_device *phydev)
+ val &= ~DP83867_CFG4_PORT_MIRROR_EN;
+
+ phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
+- phydev->addr, val);
++ phydev->addr, val);
+
+ return 0;
+ }
+@@ -211,57 +218,57 @@ static int dp83867_config_port_mirroring(struct phy_device *phydev)
+ static int dp83867_of_init(struct phy_device *phydev)
+ {
+ struct dp83867_private *dp83867 = phydev->priv;
+- ofnode node;
++ struct udevice *dev = phydev->dev;
++ int node = dev_of_offset(dev);
++ const void *fdt = gd->fdt_blob;
+ u16 val;
+
+ /* Optional configuration */
+
+- /*
+- * Keep the default value if ti,clk-output-sel is not set
++ /* Keep the default value if ti,clk-output-sel is not set
+ * or to high
+ */
++ dp83867->clk_output_sel = fdtdec_get_uint(fdt, node,
++ "ti,clk-output-sel", DP83867_CLK_O_SEL_REF_CLK);
+
+- dp83867->clk_output_sel =
+- ofnode_read_u32_default(node, "ti,clk-output-sel",
+- DP83867_CLK_O_SEL_REF_CLK);
+-
+- node = phy_get_ofnode(phydev);
+- if (!ofnode_valid(node))
+- return -EINVAL;
+-
+- if (ofnode_read_bool(node, "ti,max-output-impedance"))
++ if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance"))
+ dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
+- else if (ofnode_read_bool(node, "ti,min-output-impedance"))
++ else if (fdtdec_get_bool(fdt, node, "ti,min-output-impedance"))
+ dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
+ else
+ dp83867->io_impedance = -EINVAL;
+
+- if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
+- dp83867->rxctrl_strap_quirk = true;
+- dp83867->rx_id_delay = ofnode_read_u32_default(node,
+- "ti,rx-internal-delay",
+- -1);
++ dp83867->rxctrl_strap_quirk = fdtdec_get_bool(fdt, node,
++ "ti,dp83867-rxctrl-strap-quirk");
++
++ dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
++ "ti,rx-internal-delay", -1);
+
+- dp83867->tx_id_delay = ofnode_read_u32_default(node,
+- "ti,tx-internal-delay",
+- -1);
++ dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
++ "ti,tx-internal-delay", -1);
+
+- dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
+- -1);
+- if (ofnode_read_bool(node, "enet-phy-lane-swap"))
++ if (fdtdec_get_bool(fdt, node, "enet-phy-lane-swap"))
+ dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
+
+- if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
++ if (fdtdec_get_bool(fdt, node, "enet-phy-lane-no-swap"))
+ dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
+
++ dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
++ "ti,fifo-depth", -1);
+
+ /* Clock output selection if muxing property is set */
+ if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
+ val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
+ DP83867_DEVADDR, phydev->addr);
+- val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
+- val |= (dp83867->clk_output_sel <<
+- DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
++
++ if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
++ val |= DP83867_IO_MUX_CFG_CLK_O_DISABLE;
++ } else {
++ val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
++ val |= (dp83867->clk_output_sel <<
++ DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
++ }
++
+ phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
+ DP83867_DEVADDR, phydev->addr, val);
+ }
+@@ -306,19 +313,24 @@ static int dp83867_config(struct phy_device *phydev)
+ phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
+ val | DP83867_SW_RESTART);
+
+- /* Mode 1 or 2 workaround */
++ /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
+ if (dp83867->rxctrl_strap_quirk) {
+ val = phy_read_mmd_indirect(phydev, DP83867_CFG4,
+- DP83867_DEVADDR, phydev->addr);
++ DP83867_DEVADDR, phydev->addr);
+ val &= ~BIT(7);
+- phy_write_mmd_indirect(phydev, DP83867_CFG4,
+- DP83867_DEVADDR, phydev->addr, val);
++ phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
++ phydev->addr, val);
+ }
+
+ if (phy_interface_is_rgmii(phydev)) {
++ val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
++ if (val < 0)
++ return val;
++ val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
++ val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
+- (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
+- (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
++ val);
++
+ if (ret)
+ goto err_out;
+
+@@ -333,13 +345,11 @@ static int dp83867_config(struct phy_device *phydev)
+ */
+
+ bs = phy_read_mmd_indirect(phydev, DP83867_STRAP_STS1,
+- DP83867_DEVADDR, phydev->addr);
+- val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
+- if (bs & DP83867_STRAP_STS1_RESERVED) {
++ DP83867_DEVADDR, phydev->addr);
++ if (bs & DP83867_STRAP_STS1_RESERVED)
+ val &= ~DP83867_PHYCR_RESERVED_MASK;
+- phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
+- val);
+- }
++
++ phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, val);
+
+ } else if (phy_interface_is_sgmii(phydev)) {
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
+@@ -406,6 +416,13 @@ static int dp83867_config(struct phy_device *phydev)
+ if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
+ dp83867_config_port_mirroring(phydev);
+
++ /* Disable FORCE_LINK_GOOD */
++ val = phy_read(phydev, phydev->addr, MII_DP83867_PHYCTRL);
++ if (val & MII_DP83867_PHYCTRL_FORCE_LINK_GOOD) {
++ val &= ~(MII_DP83867_PHYCTRL_FORCE_LINK_GOOD);
++ phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, val);
++ }
++
+ genphy_config_aneg(phydev);
+ return 0;
+
+diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
+index b4beaa7..65f343f 100644
+--- a/include/configs/stm32mp1.h
++++ b/include/configs/stm32mp1.h
+@@ -155,6 +155,7 @@
+ #else /* CONFIG_STM32MP1_OPTEE */
+
+ #define STM32MP_MTDPARTS \
++ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+ "mtdparts_nor0=256k(fsbl1),256k(fsbl2),2m(ssbl),256k(logo),-(nor_user)\0" \
+ "mtdparts_nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),-(UBI)\0"
+
+@@ -189,3 +190,4 @@
+ #endif /* ifdef CONFIG_DISTRO_DEFAULTS*/
+
+ #endif /* __CONFIG_H */
++
+diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h
+index 85d08f6..3a0b451 100644
+--- a/include/dt-bindings/net/ti-dp83867.h
++++ b/include/dt-bindings/net/ti-dp83867.h
+@@ -46,4 +46,6 @@
+ #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB
+ #define DP83867_CLK_O_SEL_REF_CLK 0xC
+
++/* Special flag to indicate clock should be off */
++#define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF
+ #endif
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp/README.HOW_TO.txt b/dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp/README.HOW_TO.txt
new file mode 100644
index 0000000..952971c
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp/README.HOW_TO.txt
@@ -0,0 +1,268 @@
+Compilation of U-Boot:
+1. Pre-requisite
+2. Initialise cross-compilation via SDK
+3. Prepare U-Boot source code
+4. Management of U-Boot source code
+5. Compile U-Boot source code
+6. Update software on board
+
+1. Pre-requisite:
+-----------------
+OpenSTLinux SDK must be installed.
+
+For U-Boot build you need to install:
+* libncurses and libncursesw dev package
+ - Ubuntu: sudo apt-get install libncurses5-dev libncursesw5-dev
+ - Fedora: sudo yum install ncurses-devel
+* git:
+ - Ubuntu: sudo apt-get install git-core gitk
+ - Fedora: sudo yum install git
+
+If you have never configured you git configuration:
+ $> git config --global user.name "your_name"
+ $> git config --global user.email "your_email@example.com"
+
+2. Initialize cross-compilation via SDK:
+---------------------------------------
+* Source SDK environment:
+ $> source <path to SDK>/environment-setup-cortexa7t2hf-neon-vfpv4-openstlinux_weston-linux-gnueabi
+
+* To verify if you cross-compilation environment are put in place:
+ $> set | grep CROSS
+ CROSS_COMPILE=arm-openstlinux_weston-linux-gnueabi-
+
+Warning: the environment are valid only on the shell session where you have
+ sourced the sdk environment.
+
+3. Prepare U-Boot source:
+------------------------
+
+Extract the sources from tarball, for example:
+$> tar xfJ SOURCES-st-image-weston-openstlinux-weston-stm32mp1-*.tar.xz
+
+In the U-Boot source directory (sources/*/u-boot-stm32mp-2018.11-r0),
+you have one U-Boot source tarball, the patches and one Makefile:
+ - v2018.11.tar.gz
+ - 000*.patch
+ - Makefile.sdk
+
+NB: if you would like to have a git management on the code see
+ section 4 [Management of U-Boot source code with GIT]
+
+Then you must extract the tarball and apply the patch:
+
+ $> tar xfz v2018.11.tar.gz
+ $> cd u-boot-2018.11
+ $> for p in `ls -1 ../*.patch`; do patch -p1 < $p; done
+
+4. Management of U-Boot source code with GIT
+--------------------------------------------
+If you like to have a better management of change made on U-Boot source,
+you have 3 solutions to use git
+
+4.1 Get STMicroelectronics U-Boot source from GitHub
+
+ URL: https://github.com/STMicroelectronics/u-boot.git
+ Branch: v2018.11-stm32mp
+ Revision: v2018.11-stm32mp-r2
+
+ $> git clone https://github.com/STMicroelectronics/u-boot.git
+ $> git checkout -b WORKING v2018.11-stm32mp-r2
+
+4.2 Create Git from tarball
+
+ $> tar xvf v2018.11.tar.gz
+ $> cd u-boot-2018.11
+ $> test -d .git || git init . && git add . && git commit -m "U-Boot source code" && git gc
+ $> git checkout -b WORKING
+ $> for p in `ls -1 ../*.patch`; do git am $p; done
+
+4.3 Get Git from community and apply STMicroelectronics patches
+
+ URL: git://git.denx.de/u-boot.git
+ Branch: master
+ Revision: v2018.11
+
+ $> git clone git://git.denx.de/u-boot.git
+or
+ $> git clone http://git.denx.de/u-boot.git
+
+ $> cd u-boot
+ $> git checkout -b WORKING v2018.11
+ $> for p in `ls -1 ../*.patch`; do git am $p; done
+
+5. Compilation U-Boot source code:
+----------------------------------
+To compile U-Boot source code, first move to U-Boot source:
+ $> cd u-boot-2018.11
+ or
+ $> cd u-boot
+
+5.1 Compilation for one target (one defconfig, one device tree)
+
+ see <U-Boot source>/board/st/stm32mp1/README for details
+
+ # make stm32mp15_<config>_defconfig
+ # make DEVICE_TREE=<device tree> all
+
+ example:
+
+ a) trusted boot on ev1
+ # make stm32mp15_trusted_defconfig
+ # make DEVICE_TREE=stm32mp157c-ev1 all
+
+ b) basic boot on dk2
+ # make stm32mp15_basic_defconfig
+ # make DEVICE_TREE=stm32mp157c-dk2 all
+
+5.2 Compilation for several targets: use Makefile.sdk
+
+Calls the specific 'Makefile.sdk' provided to compile U-Boot:
+ - Display 'Makefile.sdk' file default configuration and targets:
+ $> make -f $PWD/../Makefile.sdk help
+ - Compile default U-Boot configuration:
+ $> make -f $PWD/../Makefile.sdk all
+
+Default U-Boot configuration is done in 'Makefile.sdk' file through two specific
+variables 'DEVICE_TREE' and 'UBOOT_CONFIGS':
+ - 'DEVICE_TREE' is a list of device tree to build, using 'space' as separator.
+ ex: DEVICE_TREE="<devicetree1> <devicetree2>"
+ - 'UBOOT_CONFIGS' is a list of '<defconfig>,<type>,<binary>' configurations,
+ <defconfig> is the u-boot defconfig to use to build
+ <type> is the name append to u-boot binaries (ex: 'trusted', 'basic', etc)
+ <binary> is the u-boot binary to export (ex: 'u-boot.bin', 'u-boot.stm32', etc)
+ ex: UBOOT_CONFIGS="<defconfig1>,basic,u-boot.bin <defconfig1>,trusted,u-boot.stm32"
+
+The generated binary files are available in ../build-${config}.
+
+by default we define 3 configs: basic, trusted, optee
+for the 4 board : stm32mp157a-dk1 stm32mp157c-dk2 stm32mp157c-ed1 stm32mp157c-ev1
+
+The generated files are:
+
+../build-trusted
+ u-boot-stm32mp157a-dk1-trusted.stm32
+ u-boot-stm32mp157c-dk2-trusted.stm32
+ u-boot-stm32mp157c-ed1-trusted.stm32
+ u-boot-stm32mp157c-ev1-trusted.stm32
+
+../build-optee
+ u-boot-stm32mp157a-dk1-optee.stm32
+ u-boot-stm32mp157c-dk2-optee.stm32
+ u-boot-stm32mp157c-ed1-optee.stm32
+ u-boot-stm32mp157c-ev1-optee.stm32
+
+../build-basic
+ u-boot-stm32mp157a-dk1-basic.img & u-boot-spl.stm32-stm32mp157a-dk1-basic
+ u-boot-stm32mp157c-dk2-basic.img & u-boot-spl.stm32-stm32mp157c-dk2-basic
+ u-boot-stm32mp157c-ed1-basic.img & u-boot-spl.stm32-stm32mp157c-ed1-basic
+ u-boot-stm32mp157c-ev1-basic.img & u-boot-spl.stm32-stm32mp157c-ev1-basic
+
+You can override the default U-Boot configuration if you specify these variables:
+ - Compile default U-Boot configuration but applying specific devicetree(s):
+ $> make -f $PWD/../Makefile.sdk all DEVICE_TREE="<devicetree1> <devicetree2>"
+ - Compile for a specific U-Boot configuration:
+ $> make -f $PWD/../Makefile.sdk all UBOOT_CONFIGS=<u-boot defconfig>,<u-boot type>,<u-boot binary>
+ - Compile for a specific U-Boot configuration and applying specific devicetree(s):
+ $> make -f $PWD/../Makefile.sdk all UBOOT_CONFIGS=<u-boot defconfig>,<u-boot type>,<u-boot binary> DEVICE_TREE="<devicetree1> <devicetree2>"
+
+6. Update software on board:
+----------------------------
+
+see also <U-Boot source>/board/st/stm32mp1/README
+
+6.1. partitioning of binaries:
+------------------------------
+
+There are two possible boot chains available:
+- Basic boot chain (for basic configuration)
+- Trusted boot chain (for trusted and optee configuration)
+
+U-Boot build provides binaries for each configuration:
+- Basic boot chain: U-Boot SPL and U-Boot imgage (for FSBL and SSBL)
+- Trusted boot chain: U-Boot binary with ".stm32" extension (for SSBL, FSBL is provided by TF-A)
+
+6.1.1. Basic boot chain:
+On this configuration, we use U-Boot SPL as First Stage Boot Loader (FSBL) and
+U-Boot as Second Stage Boot Loader (SSBL).
+U-Boot SPL (u-boot-spl.stm32-*) MUST be copied on a dedicated partition named "fsbl1"
+U-Boot image (u-boot*.img) MUST be copied on a dedicated partition named "ssbl"
+
+6.1.2. Trusted boot chain:
+On this configuration, U-Boot is associated to Trusted Firmware (TF-A) and only
+U-Boot image is used as Second Stage Boot Loader (SSBL).
+TF-A binary (tf-a-*.stm32) MUST be copied on a dedicated partition named "fsbl1"
+U-boot binary (u-boot*.stm32) MUST be copied on a dedicated partition named "ssbl"
+
+6.2. Update via SDCARD:
+-----------------------
+
+6.2.1. Basic boot chain
+* u-boot-spl.stm32-*
+ Copy the binary on the dedicated partition, on SDCARD/USB disk the partition
+ "fsbl1" is the partition 1:
+ - SDCARD: /dev/mmcblkXp1 (where X is the instance number)
+ - SDCARD via USB reader: /dev/sdX1 (where X is the instance number)
+ dd if=<U-Boot SPL file> of=/dev/<device partition> bs=1M conv=fdatasync
+
+* u-boot*.img
+ Copy the binary on the dedicated partition, on SDCARD/USB disk the partition
+ "ssbl" is the partition 4:
+ - SDCARD: /dev/mmcblkXp3 (where X is the instance number)
+ - SDCARD via USB reader: /dev/sdX3 (where X is the instance number)
+ dd if=<U-Boot image file> of=/dev/<device partition> bs=1M conv=fdatasync
+
+6.2.2. Trusted boot chain
+* tf-a-*.stm32
+ Copy the binary on the dedicated partition, on SDCARD/USB disk the partition
+ "fsbl1" is the partition 1:
+ - SDCARD: /dev/mmcblkXp1 (where X is the instance number)
+ - SDCARD via USB reader: /dev/sdX1 (where X is the instance number)
+ dd if=<TF-A binary file> of=/dev/<device partition> bs=1M conv=fdatasync
+
+* u-boot*.stm32
+ Copy the binary on the dedicated partition, on SDCARD/USB disk the partition
+ "ssbl" is the partition 4:
+ - SDCARD: /dev/mmcblkXp3 (where X is the instance number)
+ - SDCARD via USB reader: /dev/sdX3 (where X is the instance number)
+ dd if=<U-Boot stm32 binary file> of=/dev/<device partition> bs=1M conv=fdatasync
+
+6.2.3. FAQ
+to found the partition associated to a specific label, just plug the
+SDCARD/USB disk on your PC and call the following command:
+ $> ls -l /dev/disk/by-partlabel/
+total 0
+lrwxrwxrwx 1 root root 10 Jan 17 17:38 bootfs -> ../../mmcblk0p4
+lrwxrwxrwx 1 root root 10 Jan 17 17:38 fsbl1 -> ../../mmcblk0p1 ➔ FSBL (TF-A)
+lrwxrwxrwx 1 root root 10 Jan 17 17:38 fsbl2 -> ../../mmcblk0p2 ➔ FSBL backup (TF-A backup – same content as FSBL)
+lrwxrwxrwx 1 root root 10 Jan 17 17:38 rootfs -> ../../mmcblk0p5
+lrwxrwxrwx 1 root root 10 Jan 17 17:38 ssbl -> ../../mmcblk0p3 ➔ SSBL (U-Boot)
+lrwxrwxrwx 1 root root 10 Jan 17 17:38 userfs -> ../../mmcblk0p6
+
+6.3. Update via USB mass storage on U-Boot:
+-------------------------------------------
+
+We are using the U-Boot command ums
+
+STM32MP> help ums
+ ums - Use the UMS [USB Mass Storage]
+
+ Usage:
+ ums <USB_controller> [<devtype>] <dev[:part]> e.g. ums 0 mmc 0
+ devtype defaults to mmc
+ ums <USB controller> <dev type: mmc|usb> <dev[:part]>
+
+By default on STMicroelectronics board, "mmc 0" is SD card on SDMMC1.
+
+* Plug the SDCARD on Board.
+* Start the board and stop on U-Boot shell:
+ Hit any key to stop autoboot: 0
+ STM32MP>
+* plug an USB cable between the PC and the board via USB OTG port.
+* On U-Boot shell, call the usb mass storage functionality:
+ STM32MP> ums 0 mmc 0
+* After a delay (of up to 15 seconds), the host sees the exported block device.
+* Follow section 6.2 to put U-Boot SPL binary and U-Boot binary
+ (*.img or *.stm32) on SDCARD/USB disk.
+
+PS: A Ctrl-C is needed to stop the command.
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp_2018.11.bbappend b/dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp_2018.11.bbappend
new file mode 100644
index 0000000..3de118d
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-bsp/u-boot/u-boot-stm32mp_2018.11.bbappend
@@ -0,0 +1,5 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+
+SRC_URI += " \
+ file://0009-ARM-v2018.11-stm32mp-r2-add-phycore-stm32mp1xx-alpha1-machine.patch \
+ "
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-extended/m4projects/m4projects-stm32mp1.bbappend b/dynamic-layers/stm-st-stm32mp/recipes-extended/m4projects/m4projects-stm32mp1.bbappend
new file mode 100644
index 0000000..2ba3053
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-extended/m4projects/m4projects-stm32mp1.bbappend
@@ -0,0 +1,39 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+GIT_URL = "git://git.phytec.de/STM32CubeMP1"
+BRANCH = "1.0.0-phy"
+SRC_URI = "\
+ ${GIT_URL};branch=${BRANCH} \
+ file://Makefile.stm32 \
+ file://parse_project_config.py \
+ file://st-m4firmware-load-default.sh \
+ file://st-m4firmware-load.service \
+"
+SRCREV = "6f54fa63552de269c2c9baf8cba28c51efdb2548"
+
+PROJECTS_LIST_PHY = " \
+ 'STM32MP157C-PHY/Examples/ADC/ADC_SingleConversion_TriggerTimer_DMA' \
+ 'STM32MP157C-PHY/Examples/Cortex/CORTEXM_MPU' \
+ 'STM32MP157C-PHY/Examples/CRC/CRC_UserDefinedPolynomial' \
+ 'STM32MP157C-PHY/Examples/CRYP/CRYP_AES_DMA' \
+ 'STM32MP157C-PHY/Examples/DMA/DMA_FIFOMode' \
+ 'STM32MP157C-PHY/Examples/GPIO/GPIO_EXTI' \
+ 'STM32MP157C-PHY/Examples/HASH/HASH_SHA224SHA256_DMA' \
+ 'STM32MP157C-PHY/Examples/I2C/I2C_TwoBoards_ComIT' \
+ 'STM32MP157C-PHY/Examples/LPTIM/LPTIM_PulseCounter' \
+ 'STM32MP157C-PHY/Examples/SPI/SPI_FullDuplex_ComDMA_Master' \
+ 'STM32MP157C-PHY/Examples/SPI/SPI_FullDuplex_ComDMA_Slave' \
+ 'STM32MP157C-PHY/Examples/SPI/SPI_FullDuplex_ComIT_Master' \
+ 'STM32MP157C-PHY/Examples/SPI/SPI_FullDuplex_ComIT_Slave' \
+ 'STM32MP157C-PHY/Examples/TIM/TIM_DMABurst' \
+ 'STM32MP157C-PHY/Examples/UART/UART_TwoBoards_ComDMA' \
+ 'STM32MP157C-PHY/Examples/UART/UART_TwoBoards_ComIT' \
+ 'STM32MP157C-PHY/Examples/WWDG/WWDG_Example' \
+ 'STM32MP157C-PHY/Applications/OpenAMP/OpenAMP_raw' \
+ 'STM32MP157C-PHY/Applications/OpenAMP/OpenAMP_TTY_echo' \
+ 'STM32MP157C-PHY/Applications/OpenAMP/OpenAMP_TTY_echo_wakeup' \
+ 'STM32MP157C-PHY/Applications/FreeRTOS/FreeRTOS_ThreadCreation' \
+"
+
+PROJECTS_LIST_append = " ${PROJECTS_LIST_PHY}"
+
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/4.19.9/0065-ARM-stm32mp1-r0-rc1-add-phycore-stm32mp1xx-alpha1-machine.patch b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/4.19.9/0065-ARM-stm32mp1-r0-rc1-add-phycore-stm32mp1xx-alpha1-machine.patch
new file mode 100644
index 0000000..987bc52
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/4.19.9/0065-ARM-stm32mp1-r0-rc1-add-phycore-stm32mp1xx-alpha1-machine.patch
@@ -0,0 +1,4297 @@
+diff --git a/Documentation/devicetree/bindings/rtc/rtc.txt b/Documentation/devicetree/bindings/rtc/rtc.txt
+new file mode 100644
+index 0000000..e1c8406
+--- /dev/null
++++ b/Documentation/devicetree/bindings/rtc/rtc.txt
+@@ -0,0 +1,38 @@
++Generic device tree bindings for Real Time Clock devices
++========================================================
++
++This document describes generic bindings which can be used to describe Real Time
++Clock devices in a device tree.
++
++Required properties
++-------------------
++
++- compatible : name of RTC device following generic names recommended practice.
++
++For other required properties e.g. to describe register sets,
++clocks, etc. check the binding documentation of the specific driver.
++
++Optional properties
++-------------------
++
++- start-year : if provided, the default hardware range supported by the RTC is
++ shifted so the first usable year is the specified one.
++
++The following properties may not be supported by all drivers. However, if a
++driver wants to support one of the below features, it should adapt the bindings
++below.
++- trickle-resistor-ohms : Selected resistor for trickle charger. Should be given
++ if trickle charger should be enabled
++- backup-switchover-mode : Configure RTC backup power supply switch behaviour
++
++Trivial RTCs
++------------
++
++This is a list of trivial RTC devices that have simple device tree
++bindings, consisting only of a compatible field, an address and
++possibly an interrupt line.
++
++
++Compatible Vendor / Chip
++========== =============
++microcrystal,rv3028 Real Time Clock Module with I2C-Bus
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 5665290..77bfd4f 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -929,7 +929,10 @@ dtb-$(CONFIG_ARCH_STM32) += \
+ stm32mp157c-ed1.dtb \
+ stm32mp157c-ev1.dtb \
+ stm32mp157c-ev1-a7-examples.dtb \
+- stm32mp157c-ev1-m4-examples.dtb
++ stm32mp157c-ev1-m4-examples.dtb \
++ phycore-stm32mp1-1.dtb \
++ phycore-stm32mp1-1-a7-examples.dtb \
++ phycore-stm32mp1-1-m4-examples.dtb
+ dtb-$(CONFIG_MACH_SUN4I) += \
+ sun4i-a10-a1000.dtb \
+ sun4i-a10-ba10-tvbox.dtb \
+diff --git a/arch/arm/boot/dts/phycore-stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/phycore-stm32mp157-pinctrl.dtsi
+new file mode 100644
+index 0000000..6d569b8
+--- /dev/null
++++ b/arch/arm/boot/dts/phycore-stm32mp157-pinctrl.dtsi
+@@ -0,0 +1,1564 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
++ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
++ */
++#include <dt-bindings/pinctrl/stm32-pinfunc.h>
++
++/ {
++ soc {
++ pinctrl: pin-controller@50002000 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "st,stm32mp157-pinctrl";
++ ranges = <0 0x50002000 0xa400>;
++ interrupt-parent = <&exti>;
++ st,syscfg = <&exti 0x60 0xff>;
++ hwlocks = <&hsem 0>;
++ pins-are-numbered;
++
++ gpioa: gpio@50002000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x0 0x400>;
++ clocks = <&rcc GPIOA>;
++ st,bank-name = "GPIOA";
++ status = "disabled";
++ };
++
++ gpiob: gpio@50003000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x1000 0x400>;
++ clocks = <&rcc GPIOB>;
++ st,bank-name = "GPIOB";
++ status = "disabled";
++ };
++
++ gpioc: gpio@50004000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x2000 0x400>;
++ clocks = <&rcc GPIOC>;
++ st,bank-name = "GPIOC";
++ status = "disabled";
++ };
++
++ gpiod: gpio@50005000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x3000 0x400>;
++ clocks = <&rcc GPIOD>;
++ st,bank-name = "GPIOD";
++ status = "disabled";
++ };
++
++ gpioe: gpio@50006000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x4000 0x400>;
++ clocks = <&rcc GPIOE>;
++ st,bank-name = "GPIOE";
++ status = "disabled";
++ };
++
++ gpiof: gpio@50007000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x5000 0x400>;
++ clocks = <&rcc GPIOF>;
++ st,bank-name = "GPIOF";
++ status = "disabled";
++ };
++
++ gpiog: gpio@50008000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x6000 0x400>;
++ clocks = <&rcc GPIOG>;
++ st,bank-name = "GPIOG";
++ status = "disabled";
++ };
++
++ gpioh: gpio@50009000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x7000 0x400>;
++ clocks = <&rcc GPIOH>;
++ st,bank-name = "GPIOH";
++ status = "disabled";
++ };
++
++ gpioi: gpio@5000a000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x8000 0x400>;
++ clocks = <&rcc GPIOI>;
++ st,bank-name = "GPIOI";
++ status = "disabled";
++ };
++
++ gpioj: gpio@5000b000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x9000 0x400>;
++ clocks = <&rcc GPIOJ>;
++ st,bank-name = "GPIOJ";
++ status = "disabled";
++ };
++
++ gpiok: gpio@5000c000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0xa000 0x400>;
++ clocks = <&rcc GPIOK>;
++ st,bank-name = "GPIOK";
++ status = "disabled";
++ };
++
++ adc1_in6_pins_a: adc1-in6 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
++ };
++ };
++
++ cec_pins_a: cec-0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 15, AF4)>;
++ bias-disable;
++ drive-open-drain;
++ slew-rate = <0>;
++ };
++ };
++
++ cec_pins_sleep_a: cec-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
++ };
++ };
++
++ cec_pins_b: cec-1 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 6, AF5)>;
++ bias-disable;
++ drive-open-drain;
++ slew-rate = <0>;
++ };
++ };
++
++ cec_pins_sleep_b: cec-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
++ };
++ };
++
++ dac_ch1_pins_a: dac-ch1 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
++ };
++ };
++
++ dac_ch2_pins_a: dac-ch2 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
++ };
++ };
++
++ dcmi_pins_a: dcmi-0 {
++ pins {
++ pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
++ <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
++ <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
++ <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
++ <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
++ <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
++ <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
++ <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
++ <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
++ <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
++ <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
++ <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
++ <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
++ <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
++ <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
++ bias-disable;
++ };
++ };
++
++ dcmi_sleep_pins_a: dcmi-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
++ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
++ <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
++ <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
++ <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
++ <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
++ <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
++ <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
++ <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
++ <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
++ <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
++ <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
++ <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
++ <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
++ <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
++ };
++ };
++
++ dfsdm_clkout_pins_a: dfsdm-clkout-pins-0 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 13, AF3)>; /* DFSDM_CKOUT */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++ };
++
++ dfsdm_clkout_sleep_pins_a: dfsdm-clkout-sleep-pins-0 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 13, ANALOG)>; /* DFSDM_CKOUT */
++ };
++ };
++
++ dfsdm_data1_pins_a: dfsdm-data1-pins-0 {
++ pins {
++ pinmux = <STM32_PINMUX('C', 3, AF3)>; /* DFSDM_DATA1 */
++ };
++ };
++
++ dfsdm_data1_sleep_pins_a: dfsdm-data1-sleep-pins-0 {
++ pins {
++ pinmux = <STM32_PINMUX('C', 3, ANALOG)>; /* DFSDM_DATA1 */
++ };
++ };
++
++ dfsdm_data3_pins_a: dfsdm-data3-pins-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 13, AF6)>; /* DFSDM_DATA3 */
++ };
++ };
++
++ dfsdm_data3_sleep_pins_a: dfsdm-data3-sleep-pins-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 13, ANALOG)>; /* DFSDM_DATA3 */
++ };
++ };
++
++ ethernet0_rgmii_pins_a: rgmii-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
++ <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
++ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
++ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
++ <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
++ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
++ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
++ <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
++ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
++ <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
++ <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
++ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
++ <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
++ bias-disable;
++ };
++ };
++
++ ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
++ <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
++ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
++ <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
++ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
++ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
++ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
++ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
++ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
++ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
++ <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
++ <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
++ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
++ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
++ };
++ };
++
++ fmc_pins_a: fmc-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
++ <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
++ <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
++ <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
++ <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
++ <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
++ <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
++ <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
++ <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
++ <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
++ <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
++ <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
++ <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
++ bias-pull-up;
++ };
++ };
++
++ fmc_sleep_pins_a: fmc-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
++ <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
++ <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
++ <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
++ <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
++ <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
++ <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
++ <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
++ <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
++ <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
++ <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
++ <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
++ <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
++ <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
++ };
++ };
++
++ hdp0_pins_a: hdp0-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 12, AF2)>; /* HDP0 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp0_pins_sleep_a: hdp0-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 12, ANALOG)>; /* HDP0 */
++ };
++ };
++
++ hdp0_pins_b: hdp0-1 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 10, AF0)>; /* HDP0 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp0_pins_sleep_b: hdp0-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 10, ANALOG)>; /* HDP0 */
++ };
++ };
++
++ hdp1_pins_a: hdp1-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 13, AF2)>; /* HDP1 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp1_pins_sleep_a: hdp1-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 13, ANALOG)>; /* HDP1 */
++ };
++ };
++
++ hdp1_pins_b: hdp1-1 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 9, AF0)>; /* HDP1 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp1_pins_sleep_b: hdp1-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 9, ANALOG)>; /* HDP1 */
++ };
++ };
++
++ hdp2_pins_a: hdp2-0 {
++ pins {
++ pinmux = <STM32_PINMUX('J', 5, AF2)>; /* HDP2 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp2_pins_sleep_a: hdp2-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('J', 5, ANALOG)>; /* HDP2 */
++ };
++ };
++
++ hdp2_pins_b: hdp2-1 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 13, AF0)>; /* HDP2 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp2_pins_sleep_b: hdp2-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 13, ANALOG)>; /* HDP2 */
++ };
++ };
++
++ hdp3_pins_a: hdp3-0 {
++ pins {
++ pinmux = <STM32_PINMUX('J', 6, AF2)>; /* HDP3 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp3_pins_sleep_a: hdp3-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('J', 6, ANALOG)>; /* HDP3 */
++ };
++ };
++
++ hdp3_pins_b: hdp3-1 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 15, AF0)>; /* HDP3 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp3_pins_sleep_b: hdp3-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 15, ANALOG)>; /* HDP3 */
++ };
++ };
++
++ hdp4_pins_a: hdp4-0 {
++ pins {
++ pinmux = <STM32_PINMUX('K', 1, AF2)>; /* HDP4 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp4_pins_sleep_a: hdp4-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('K', 1, ANALOG)>; /* HDP4 */
++ };
++ };
++
++ hdp4_pins_b: hdp4-1 {
++ pins {
++ pinmux = <STM32_PINMUX('C', 7, AF0)>; /* HDP4 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp4_pins_sleep_b: hdp4-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* HDP4 */
++ };
++ };
++
++ hdp5_pins_a: hdp5-0 {
++ pins {
++ pinmux = <STM32_PINMUX('K', 2, AF2)>; /* HDP5 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp5_pins_sleep_a: hdp5-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('K', 2, ANALOG)>; /* HDP5 */
++ };
++ };
++
++ hdp5_pins_b: hdp5-1 {
++ pins {
++ pinmux = <STM32_PINMUX('D', 3, AF0)>; /* HDP5 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp5_pins_sleep_b: hdp5-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('D', 3, ANALOG)>; /* HDP5 */
++ };
++ };
++
++ hdp6_pins_a: hdp6-0 {
++ pins {
++ pinmux = <STM32_PINMUX('K', 5, AF2)>; /* HDP6 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp6_pins_sleep_a: hdp6-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('K', 5, ANALOG)>; /* HDP6 */
++ };
++ };
++
++ hdp6_pins_b: hdp6-1 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 8, AF0)>; /* HDP6 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp6_pins_sleep_b: hdp6-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 8, ANALOG)>; /* HDP6 */
++ };
++ };
++
++ hdp7_pins_a: hdp7-0 {
++ pins {
++ pinmux = <STM32_PINMUX('K', 6, AF2)>; /* HDP7 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp7_pins_sleep_a: hdp7-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('K', 6, ANALOG)>; /* HDP7 */
++ };
++ };
++
++ hdp7_pins_b: hdp7-1 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 9, AF0)>; /* HDP7 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++ };
++
++ hdp7_pins_sleep_b: hdp7-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* HDP7 */
++ };
++ };
++
++ i2c1_pins_a: i2c1-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
++ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
++ bias-disable;
++ drive-open-drain;
++ slew-rate = <0>;
++ };
++ };
++
++ i2c1_pins_sleep_a: i2c1-1 {
++ pins {
++ pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
++ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
++ };
++ };
++
++ i2c2_pins_a: i2c2-0 {
++ pins {
++ pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
++ <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
++ bias-disable;
++ drive-open-drain;
++ slew-rate = <0>;
++ };
++ };
++
++ i2c2_pins_sleep_a: i2c2-1 {
++ pins {
++ pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
++ <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
++ };
++ };
++
++ i2s2_pins_a: i2s2-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
++ <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
++ <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-disable;
++ };
++ };
++
++ i2s2_pins_sleep_a: i2s2-1 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
++ <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
++ <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
++ };
++ };
++
++ ltdc_pins_a: ltdc-a-0 {
++ pins {
++ pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
++ <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
++ <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
++ <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */
++ <STM32_PINMUX('C', 10, AF14)>, /* LCD_R2 */
++ <STM32_PINMUX('B', 0, AF9)>, /* LCD_R3 */
++ <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
++ <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */
++ <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
++ <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
++ <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
++ <STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */
++ <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
++ <STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */
++ <STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */
++ <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
++ <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
++ <STM32_PINMUX('G', 11, AF14)>, /* LCD_B3 */
++ <STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */
++ <STM32_PINMUX('I', 5, AF14)>, /* LCD_B5 */
++ <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
++ <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++ };
++
++ ltdc_pins_sleep_a: ltdc-a-1 {
++ pins {
++ pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
++ <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
++ <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
++ <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */
++ <STM32_PINMUX('C', 10, ANALOG)>, /* LCD_R2 */
++ <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_R3 */
++ <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
++ <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */
++ <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
++ <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
++ <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
++ <STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */
++ <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
++ <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */
++ <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */
++ <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
++ <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
++ <STM32_PINMUX('G', 11, ANALOG)>, /* LCD_B3 */
++ <STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */
++ <STM32_PINMUX('I', 5, ANALOG)>, /* LCD_B5 */
++ <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
++ <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
++ };
++ };
++
++ ltdc_pins_b: ltdc-b-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
++ <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
++ <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
++ <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
++ <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
++ <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
++ <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
++ <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
++ <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
++ <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
++ <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
++ <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
++ <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
++ <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
++ <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
++ <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
++ <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
++ <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
++ <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
++ <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
++ <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
++ <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
++ <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
++ <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
++ <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
++ <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
++ <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
++ <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++ };
++
++ ltdc_pins_sleep_b: ltdc-b-1 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
++ <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
++ <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
++ <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
++ <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
++ <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
++ <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
++ <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
++ <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
++ <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
++ <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
++ <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
++ <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
++ <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
++ <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
++ <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
++ <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
++ <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
++ <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
++ <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
++ <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
++ <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
++ <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
++ <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
++ <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
++ <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
++ <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
++ <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
++ };
++ };
++
++ m_can1_pins_a: m-can1-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
++ slew-rate = <0>;
++ drive-push-pull;
++ bias-disable;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
++ bias-disable;
++ };
++ };
++
++ m_can1_sleep_pins_a: m_can1-sleep@0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */
++ <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */
++ };
++ };
++
++ pwm1_pins_a: pwm1-0 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
++ <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */
++ <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */
++ bias-pull-down;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ };
++
++ pwm1_sleep_pins_a: pwm1-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
++ <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */
++ <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */
++ };
++ };
++
++ pwm2_pins_a: pwm2-0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
++ bias-pull-down;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ };
++
++ pwm2_sleep_pins_a: pwm2-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
++ };
++ };
++
++ pwm3_pins_a: pwm3-0 {
++ pins {
++ pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */
++ bias-pull-down;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ };
++
++ pwm3_sleep_pins_a: pwm3-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */
++ };
++ };
++
++ pwm4_pins_a: pwm4-0 {
++ pins {
++ pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
++ <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
++ bias-pull-down;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ };
++
++ pwm4_sleep_pins_a: pwm4-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
++ <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
++ };
++ };
++
++ pwm4_pins_b: pwm4-1 {
++ pins {
++ pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
++ bias-pull-down;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ };
++
++ pwm4_sleep_pins_b: pwm4-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
++ };
++ };
++
++ pwm5_pins_a: pwm5-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */
++ bias-pull-down;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ };
++
++ pwm5_sleep_pins_a: pwm5-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */
++ };
++ };
++
++ pwm8_pins_a: pwm8-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
++ bias-pull-down;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ };
++
++ pwm8_sleep_pins_a: pwm8-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */
++ };
++ };
++
++ qspi_bk1_pins_a: qspi-bk1-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
++ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
++ <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
++ <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
++ bias-pull-up;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++ };
++
++ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
++ <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
++ <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
++ <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
++ <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
++ };
++ };
++
++ qspi_clk_pins_a: qspi-clk-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <3>;
++ };
++ };
++
++ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
++ };
++ };
++
++ sai2a_pins_a: sai2a-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
++ <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
++ <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
++ <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
++ slew-rate = <0>;
++ drive-push-pull;
++ bias-disable;
++ };
++ };
++
++ sai2a_sleep_pins_a: sai2a-1 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
++ <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
++ <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
++ <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
++ };
++ };
++
++ sai2a_pins_b: sai2a-2 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 6, AF10)>; /* SAI2_SD_A */
++ bias-disable;
++ };
++ };
++
++ sai2a_sleep_pins_b: sai2a-3 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 6, ANALOG)>; /* SAI2_SD_A */
++ };
++ };
++
++ sai2b_pins_a: sai2b-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('H', 2, AF10)>, /* SAI2_SCK_B */
++ <STM32_PINMUX('C', 0, AF8)>, /* SAI2_FS_B */
++ <STM32_PINMUX('H', 3, AF10)>; /* SAI2_MCLK_B */
++ slew-rate = <0>;
++ drive-push-pull;
++ bias-disable;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
++ bias-disable;
++ };
++ };
++
++ sai2b_sleep_pins_a: sai2b-1 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
++ <STM32_PINMUX('H', 2, ANALOG)>, /* SAI2_SCK_B */
++ <STM32_PINMUX('C', 0, ANALOG)>, /* SAI2_FS_B */
++ <STM32_PINMUX('H', 3, ANALOG)>; /* SAI2_MCLK_B */
++ };
++ };
++
++ sai2b_pins_b: sai2b-2 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
++ bias-disable;
++ };
++ };
++
++ sai2b_sleep_pins_b: sai2b-3 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
++ };
++ };
++
++ sai4a_pins_a: sai4a-0 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
++ slew-rate = <0>;
++ drive-push-pull;
++ bias-disable;
++ };
++ };
++
++ sai4a_sleep_pins_a: sai4a-1 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
++ };
++ };
++
++ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
++ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
++ <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
++ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
++ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-disable;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
++ slew-rate = <2>;
++ drive-push-pull;
++ bias-disable;
++ };
++ };
++
++ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
++ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
++ <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
++ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-disable;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
++ slew-rate = <2>;
++ drive-push-pull;
++ bias-disable;
++ };
++ pins3 {
++ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
++ slew-rate = <1>;
++ drive-open-drain;
++ bias-disable;
++ };
++ };
++
++ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
++ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
++ <STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC1_D2 */
++ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
++ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
++ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
++ };
++ };
++
++ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
++ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
++ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
++ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
++ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
++ slew-rate = <2>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ };
++
++ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
++ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
++ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
++ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
++ slew-rate = <2>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ pins3 {
++ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
++ slew-rate = <1>;
++ drive-open-drain;
++ bias-pull-up;
++ };
++ };
++
++ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
++ <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
++ <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
++ <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
++ <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
++ <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
++ };
++ };
++
++ sdmmc2_b4_pins_b: sdmmc2-b4-1 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
++ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
++ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
++ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
++ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-disable;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
++ slew-rate = <2>;
++ drive-push-pull;
++ bias-disable;
++ };
++ };
++
++ sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
++ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
++ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
++ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-disable;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
++ slew-rate = <2>;
++ drive-push-pull;
++ bias-disable;
++ };
++ pins3 {
++ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
++ slew-rate = <1>;
++ drive-open-drain;
++ bias-disable;
++ };
++ };
++
++ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
++ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
++ <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
++ <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ };
++
++ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
++ <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
++ <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
++ <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
++ };
++ };
++
++ sdmmc3_b4_pins_a: sdmmc3-b4-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
++ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
++ <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
++ <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
++ <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
++ slew-rate = <2>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ };
++
++ sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
++ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
++ <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
++ <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
++ slew-rate = <1>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
++ slew-rate = <2>;
++ drive-push-pull;
++ bias-pull-up;
++ };
++ pins3 {
++ pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
++ slew-rate = <1>;
++ drive-open-drain;
++ bias-pull-up;
++ };
++ };
++
++ sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
++ <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
++ <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
++ <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
++ <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
++ <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
++ };
++ };
++
++ spdifrx_pins_a: spdifrx-0 {
++ pins {
++ pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
++ bias-disable;
++ };
++ };
++
++ spdifrx_sleep_pins_a: spdifrx-1 {
++ pins {
++ pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
++ };
++ };
++
++ spi4_pins_a: spi4-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
++ <STM32_PINMUX('E', 14, AF5)>; /* SPI4_MOSI */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++
++ pins2 {
++ pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
++ bias-disable;
++ };
++ };
++
++ spi4_sleep_pins_a: spi4-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 12, ANALOG)>, /* SPI4_SCK */
++ <STM32_PINMUX('E', 13, ANALOG)>, /* SPI4_MISO */
++ <STM32_PINMUX('E', 14, ANALOG)>; /* SPI4_MOSI */
++ };
++ };
++
++ spi5_pins_a: spi5-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('F', 7, AF5)>, /* SPI5_SCK */
++ <STM32_PINMUX('F', 9, AF5)>; /* SPI5_MOSI */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++
++ pins2 {
++ pinmux = <STM32_PINMUX('F', 8, AF5)>; /* SPI5_MISO */
++ bias-disable;
++ };
++ };
++
++ spi5_sleep_pins_a: spi5-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* SPI5_SCK */
++ <STM32_PINMUX('F', 8, ANALOG)>, /* SPI5_MISO */
++ <STM32_PINMUX('F', 9, ANALOG)>; /* SPI5_MOSI */
++ };
++ };
++
++ uart4_pins_a: uart4-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
++ bias-disable;
++ };
++ };
++
++ uart4_idle_pins_a: uart4-idle-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
++ bias-disable;
++ };
++ };
++
++ uart4_sleep_pins_a: uart4-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
++ <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
++ };
++ };
++
++ uart7_pins_a: uart7-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
++ bias-disable;
++ };
++ };
++
++ uart7_idle_pins_a: uart7-idle-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* USART7_TX */
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
++ bias-disable;
++ };
++ };
++
++ uart7_sleep_pins_a: uart7-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* USART7_TX */
++ <STM32_PINMUX('E', 7, ANALOG)>; /* USART7_RX */
++ };
++ };
++
++ usart3_pins_a: usart3-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
++ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
++ <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
++ bias-disable;
++ };
++ };
++
++ usart3_idle_pins_a: usart3-idle-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
++ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
++ <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
++ bias-disable;
++ };
++ };
++
++ usart3_sleep_pins_a: usart3-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
++ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
++ <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */
++ <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
++ };
++ };
++
++ usart3_pins_b: usart3-1 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
++ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
++ <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
++ bias-disable;
++ };
++ };
++
++ usart3_idle_pins_b: usart3-idle-1 {
++ pins1 {
++ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
++ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
++ <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
++ bias-disable;
++ };
++ };
++
++ usart3_sleep_pins_b: usart3-sleep-1 {
++ pins {
++ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
++ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
++ <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */
++ <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
++ };
++ };
++
++ usbotg_hs_pins_a: usbotg_hs-0 {
++ pins {
++ pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
++ };
++ };
++ };
++
++ pinctrl_z: pin-controller-z@54004000 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "st,stm32mp157-z-pinctrl";
++ ranges = <0 0x54004000 0x400>;
++ pins-are-numbered;
++ interrupt-parent = <&exti>;
++ st,syscfg = <&exti 0x60 0xff>;
++ hwlocks = <&hsem 0>;
++
++ gpioz: gpio@54004000 {
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0 0x400>;
++ clocks = <&rcc GPIOZ>;
++ st,bank-name = "GPIOZ";
++ st,bank-ioport = <11>;
++ status = "disabled";
++ };
++
++ btreg: bt_reg_on-0 {
++ pins {
++ pinmux = <STM32_PINMUX('Z', 6, GPIO)>;
++ drive-push-pull;
++ bias-pull-up;
++ output-high;
++ slew-rate = <0>;
++ };
++ };
++
++
++ usart1_pins_a: usart1-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('Z', 7, AF7)>; /* USART1_TX */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
++ bias-disable;
++ };
++ };
++
++ usart1_idle_pins_a: usart1-idle-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('Z', 7, ANALOG)>; /* USART1_TX */
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
++ bias-disable;
++ };
++ };
++
++ usart1_sleep_pins_a: usart1-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('Z', 7, ANALOG)>, /* USART1_TX */
++ <STM32_PINMUX('Z', 6, ANALOG)>; /* USART1_RX */
++ };
++ };
++
++ i2c4_pins_a: i2c4-0 {
++ pins {
++ pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
++ <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
++ bias-disable;
++ drive-open-drain;
++ slew-rate = <0>;
++ };
++ };
++
++ i2c4_pins_sleep_a: i2c4-1 {
++ pins {
++ pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
++ <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
++ };
++ };
++
++ spi1_pins_a: spi1-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
++ <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++
++ pins2 {
++ pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
++ bias-disable;
++ };
++ };
++
++ spi1_sleep_pins_a: spi1-sleep-0 {
++ pins {
++ pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */
++ <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
++ <STM32_PINMUX('B', 5, ANALOG)>; /* SPI1_MOSI */
++ };
++ };
++ };
++ };
++};
+diff --git a/arch/arm/boot/dts/phycore-stm32mp157cac-pinctrl.dtsi b/arch/arm/boot/dts/phycore-stm32mp157cac-pinctrl.dtsi
+new file mode 100644
+index 0000000..13d3583
+--- /dev/null
++++ b/arch/arm/boot/dts/phycore-stm32mp157cac-pinctrl.dtsi
+@@ -0,0 +1,78 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
++ * Author: Alexandre Torgue <alexandre.torgue@st.com>
++ */
++
++#include "phycore-stm32mp157-pinctrl.dtsi"
++/ {
++ soc {
++ pinctrl: pin-controller@50002000 {
++ st,package = <STM32MP157CAC>;
++
++ gpioa: gpio@50002000 {
++ status = "okay";
++ ngpios = <16>;
++ gpio-ranges = <&pinctrl 0 0 16>;
++ };
++
++ gpiob: gpio@50003000 {
++ status = "okay";
++ ngpios = <16>;
++ gpio-ranges = <&pinctrl 0 16 16>;
++ };
++
++ gpioc: gpio@50004000 {
++ status = "okay";
++ ngpios = <16>;
++ gpio-ranges = <&pinctrl 0 32 16>;
++ };
++
++ gpiod: gpio@50005000 {
++ status = "okay";
++ ngpios = <16>;
++ gpio-ranges = <&pinctrl 0 48 16>;
++ };
++
++ gpioe: gpio@50006000 {
++ status = "okay";
++ ngpios = <16>;
++ gpio-ranges = <&pinctrl 0 64 16>;
++ };
++
++ gpiof: gpio@50007000 {
++ status = "okay";
++ ngpios = <16>;
++ gpio-ranges = <&pinctrl 0 80 16>;
++ };
++
++ gpiog: gpio@50008000 {
++ status = "okay";
++ ngpios = <16>;
++ gpio-ranges = <&pinctrl 0 96 16>;
++ };
++
++ gpioh: gpio@50009000 {
++ status = "okay";
++ ngpios = <16>;
++ gpio-ranges = <&pinctrl 0 112 16>;
++ };
++
++ gpioi: gpio@5000a000 {
++ status = "okay";
++ ngpios = <12>;
++ gpio-ranges = <&pinctrl 0 128 12>;
++ };
++ };
++
++ pinctrl_z: pin-controller-z@54004000 {
++ st,package = <STM32MP157CAC>;
++
++ gpioz: gpio@54004000 {
++ status = "okay";
++ ngpios = <8>;
++ gpio-ranges = <&pinctrl_z 0 400 8>;
++ };
++ };
++ };
++};
+diff --git a/arch/arm/boot/dts/phycore-stm32mp157cac-som.dtsi b/arch/arm/boot/dts/phycore-stm32mp157cac-som.dtsi
+new file mode 100644
+index 0000000..8d5b382
+--- /dev/null
++++ b/arch/arm/boot/dts/phycore-stm32mp157cac-som.dtsi
+@@ -0,0 +1,375 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++/dts-v1/;
++
++#include "stm32mp157c.dtsi"
++#include "stm32mp157c-m4-srm.dtsi"
++#include "phycore-stm32mp157cac-pinctrl.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/mfd/st,stpmic1.h>
++#include <dt-bindings/net/ti-dp83867.h>
++#include <dt-bindings/rtc/rtc-stm32.h>
++
++
++/ {
++ model = "Phytec GmbH phycore-stm32mp1-1 SOM";
++ compatible = "phytec,PCM-068-1534-0-005", "st,stm32mp157";
++
++ memory@c0000000 {
++ reg = <0xc0000000 0x20000000>;
++ };
++
++ reserved-memory {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ retram: retram@0x38000000 {
++ compatible = "shared-dma-pool";
++ reg = <0x38000000 0x10000>;
++ no-map;
++ };
++
++ mcuram: mcuram@0x30000000 {
++ compatible = "shared-dma-pool";
++ reg = <0x30000000 0x40000>;
++ no-map;
++ };
++
++ mcuram2: mcuram2@0x10000000 {
++ compatible = "shared-dma-pool";
++ reg = <0x10000000 0x40000>;
++ no-map;
++ };
++
++ vdev0vring0: vdev0vring0@10040000 {
++ compatible = "shared-dma-pool";
++ reg = <0x10040000 0x2000>;
++ no-map;
++ };
++
++ vdev0vring1: vdev0vring1@10042000 {
++ compatible = "shared-dma-pool";
++ reg = <0x10042000 0x2000>;
++ no-map;
++ };
++
++ vdev0buffer: vdev0buffer@10044000 {
++ compatible = "shared-dma-pool";
++ reg = <0x10044000 0x4000>;
++ no-map;
++ };
++
++ gpu_reserved: gpu@f8000000 {
++ reg = <0xf8000000 0x8000000>;
++ no-map;
++ };
++ };
++
++ sram: sram@10050000 {
++ compatible = "mmio-sram";
++ reg = <0x10050000 0x10000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 0x10050000 0x10000>;
++
++ dma_pool: dma_pool@0 {
++ reg = <0x0 0x10000>;
++ pool;
++ };
++ };
++};
++
++&dma1 {
++ sram = <&dma_pool>;
++};
++
++&dma2 {
++ sram = <&dma_pool>;
++};
++
++&dts {
++ status = "okay";
++};
++
++&gpu {
++ contiguous-area = <&gpu_reserved>;
++ status = "okay";
++};
++
++&i2c4 {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&i2c4_pins_a>;
++ pinctrl-1 = <&i2c4_pins_sleep_a>;
++ i2c-scl-rising-time-ns = <185>;
++ i2c-scl-falling-time-ns = <20>;
++ status = "okay";
++ /delete-property/dmas;
++ /delete-property/dma-names;
++
++ pmic: stpmic@33 {
++ compatible = "st,stpmic1";
++ reg = <0x33>;
++ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ status = "okay";
++
++ st,main-control-register = <0x04>;
++ st,vin-control-register = <0xc0>;
++ st,usb-control-register = <0x20>;
++
++ regulators {
++ compatible = "st,stpmic1-regulators";
++
++ ldo1-supply = <&v3v3>;
++ ldo2-supply = <&v3v3>;
++ ldo3-supply = <&vdd_ddr>;
++ ldo5-supply = <&v3v3>;
++ ldo6-supply = <&v3v3>;
++ pwr_sw1-supply = <&bst_out>;
++ pwr_sw2-supply = <&bst_out>;
++
++ vddcore: buck1 {
++ regulator-name = "vddcore";
++ regulator-min-microvolt = <1200000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-always-on;
++ regulator-initial-mode = <0>;
++ regulator-over-current-protection;
++ };
++
++ vdd_ddr: buck2 {
++ regulator-name = "vdd_ddr";
++ regulator-min-microvolt = <1350000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-always-on;
++ regulator-initial-mode = <0>;
++ regulator-over-current-protection;
++ };
++
++ vdd: buck3 {
++ regulator-name = "vdd";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ st,mask-reset;
++ regulator-initial-mode = <0>;
++ regulator-over-current-protection;
++ };
++
++ v3v3: buck4 {
++ regulator-name = "v3v3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ regulator-over-current-protection;
++ regulator-initial-mode = <0>;
++ };
++
++ v1v8_audio: ldo1 {
++ regulator-name = "v1v8_audio";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ interrupts = <IT_CURLIM_LDO1 0>;
++
++ };
++
++ vdd_eth_2v5: ldo2 {
++ regulator-name = "dd_eth_2v5";
++ regulator-min-microvolt = <2500000>;
++ regulator-max-microvolt = <2500000>;
++ regulator-always-on;
++ interrupts = <IT_CURLIM_LDO2 0>;
++
++ };
++
++ vtt_ddr: ldo3 {
++ regulator-name = "vtt_ddr";
++ regulator-min-microvolt = <500000>;
++ regulator-max-microvolt = <750000>;
++ regulator-always-on;
++ regulator-over-current-protection;
++ };
++
++ vdd_usb: ldo4 {
++ regulator-name = "vdd_usb";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ interrupts = <IT_CURLIM_LDO4 0>;
++ };
++
++ vdda: ldo5 {
++ regulator-name = "vdda";
++ regulator-min-microvolt = <2900000>;
++ regulator-max-microvolt = <2900000>;
++ interrupts = <IT_CURLIM_LDO5 0>;
++ regulator-boot-on;
++ };
++
++ vdd_eth_1v0: ldo6 {
++ regulator-name = "vdd_eth_1v0";
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <1000000>;
++ regulator-always-on;
++ interrupts = <IT_CURLIM_LDO6 0>;
++
++ };
++
++ vref_ddr: vref_ddr {
++ regulator-name = "vref_ddr";
++ regulator-always-on;
++ regulator-over-current-protection;
++ };
++
++ bst_out: boost {
++ regulator-name = "bst_out";
++ interrupts = <IT_OCP_BOOST 0>;
++ };
++
++ vbus_otg: pwr_sw1 {
++ regulator-name = "vbus_otg";
++ interrupts = <IT_OCP_OTG 0>;
++ regulator-active-discharge;
++ };
++
++ vbus_sw: pwr_sw2 {
++ regulator-name = "vbus_sw";
++ interrupts = <IT_OCP_SWOUT 0>;
++ regulator-active-discharge;
++ };
++ };
++
++ onkey {
++ compatible = "st,stpmic1-onkey";
++ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
++ interrupt-names = "onkey-falling", "onkey-rising";
++ status = "okay";
++ };
++
++ watchdog {
++ compatible = "st,stpmic1-wdt";
++ status = "disabled";
++ };
++ };
++
++ eeprom@50 {
++ compatible = "microchip,24c32", "atmel,24c32";
++ reg = <0x50>;
++ };
++
++ i2c4_rtc: rtc@52 {
++ compatible = "microcrystal,rv3028";
++ reg = <0x52>;
++ /*interrupt-parent = <&gpio5>;
++ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;*/
++ backup-switchover-mode = /bits/ 8 <0x01>;
++ status = "okay";
++ };
++};
++
++&ethernet0 {
++ status = "okay";
++ pinctrl-0 = <&ethernet0_rgmii_pins_a>;
++ pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
++ pinctrl-names = "default", "sleep";
++ phy-mode = "rgmii";
++ max-speed = <1000>;
++ phy-handle = <&phy0>;
++ st,eth_clk_sel = <1>;
++
++ mdio0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "snps,dwmac-mdio";
++
++ phy0: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <1>;
++ interrupt-parent = <&gpiog>;
++ interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
++ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
++ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
++ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
++ ti,min-output-impedance;
++ enet-phy-lane-no-swap;
++ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
++ };
++ };
++};
++
++&m4_rproc {
++ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
++ <&vdev0vring1>, <&vdev0buffer>;
++ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
++ mbox-names = "vq0", "vq1", "shutdown";
++ interrupt-parent = <&exti>;
++ interrupts = <68 1>;
++ interrupt-names = "wdg";
++ recovery;
++ status = "okay";
++};
++
++&ipcc {
++ status = "okay";
++};
++
++&iwdg2 {
++ timeout-sec = <32>;
++ status = "okay";
++};
++
++&pwr {
++ pwr-supply = <&vdd>;
++};
++
++&rng1 {
++ status = "okay";
++};
++
++&rtc {
++ status = "okay";
++};
++
++&qspi {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
++ pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
++ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ flash0: w25q128@0 {
++ compatible = "winbond,w25q128", "jedec,spi-nor", "spi-flash";
++ reg = <0>;
++ spi-rx-bus-width = <4>;
++ spi-max-frequency = <50000000>;
++ m25p,fast-read;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ };
++};
++
++&sdmmc2 {
++ pinctrl-names = "default", "opendrain", "sleep";
++ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
++ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
++ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
++ non-removable;
++ no-sd;
++ no-sdio;
++ st,neg-edge;
++ bus-width = <8>;
++ vmmc-supply = <&v3v3>;
++ vqmmc-supply = <&v3v3>;
++ mmc-ddr-3_3v;
++ status = "okay";
++};
++
+diff --git a/arch/arm/boot/dts/phycore-stm32mp1-1-a7-examples.dts b/arch/arm/boot/dts/phycore-stm32mp1-1-a7-examples.dts
+new file mode 100644
+index 0000000..f9a68a7
+--- /dev/null
++++ b/arch/arm/boot/dts/phycore-stm32mp1-1-a7-examples.dts
+@@ -0,0 +1,15 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++/dts-v1/;
++
++#include "phycore-stm32mp1-1.dtsi"
++#include <dt-bindings/rtc/rtc-stm32.h>
++
++/ {
++ model = "Phytec GmbH phycore-stm32mp1-1 Dev Board";
++ compatible = "phytec,pcm939-1517-1-002", "st,phycore-stm32mp1-1-a7-examples", "st,stm32mp157";
++};
+diff --git a/arch/arm/boot/dts/phycore-stm32mp1-1-m4-examples.dts b/arch/arm/boot/dts/phycore-stm32mp1-1-m4-examples.dts
+new file mode 100644
+index 0000000..3871191
+--- /dev/null
++++ b/arch/arm/boot/dts/phycore-stm32mp1-1-m4-examples.dts
+@@ -0,0 +1,157 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++/dts-v1/;
++
++#include "phycore-stm32mp1-1.dtsi"
++#include <dt-bindings/rtc/rtc-stm32.h>
++
++/ {
++ model = "Phytec GmbH phycore-stm32mp1-1 Dev Board";
++ compatible = "phytec,pcm939-1517-1-002", "st,phycore-stm32mp1-1-m4-examples", "st,stm32mp157";
++};
++
++&adc {
++ status = "disabled";
++};
++
++&dac {
++ status = "disabled";
++};
++
++&dma2 {
++ status = "disabled";
++};
++
++&dmamux1 {
++ dma-masters = <&dma1>;
++ dma-channels = <8>;
++};
++
++&m4_adc {
++ vref-supply = <&vrefbuf>;
++ status = "okay";
++};
++
++&m4_dac {
++ status = "okay";
++};
++
++&m4_dma2 {
++ status = "okay";
++};
++
++&m4_crc2 {
++ status = "okay";
++};
++
++&m4_cryp2 {
++ status = "okay";
++};
++
++&m4_hash2 {
++ status = "okay";
++};
++
++&m4_i2c2 {
++ pinctrl-names = "rproc_default";
++ pinctrl-0 = <&i2c2_pins_a>;
++ status = "okay";
++};
++
++&m4_rng2 {
++ status = "okay";
++};
++
++&m4_rproc {
++ m4_system_resources {
++ status = "okay";
++
++ button {
++ compatible = "rproc-srm-dev";
++ interrupt-parent = <&gpioa>;
++ interrupts = <14 2>;
++ interrupt-names = "irq";
++ status = "okay";
++ };
++
++ m4_led: m4_led {
++ compatible = "rproc-srm-dev";
++ pinctrl-names = "rproc_default", "rproc_sleep";
++ pinctrl-0 = <&leds_orange_pins>;
++ pinctrl-1 = <&leds_orange_sleep_pins>;
++ status = "okay";
++ };
++ };
++};
++
++&m4_spi4 {
++ pinctrl-names = "rproc_default";
++ pinctrl-0 = <&spi4_pins_a>;
++ status = "okay";
++};
++
++
++&m4_timers2 {
++ pinctrl-names = "rproc_default";
++ status = "okay";
++};
++
++&m4_timers1 {
++ pinctrl-names = "rproc_default";
++ pinctrl-0 = <&timer1_pins>;
++ status = "okay";
++};
++
++&m4_uart7 {
++ pinctrl-names = "rproc_default";
++ pinctrl-0 = <&uart7_pins>;
++ status = "okay";
++};
++
++&pinctrl {
++ uart7_pins: uart7-test-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ pins2 {
++ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
++ bias-disable;
++ };
++ };
++
++ timer1_pins: pwm1-test-0 {
++ pins {
++ pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */
++ bias-pull-down;
++ drive-push-pull;
++ slew-rate = <0>;
++ };
++ };
++
++ leds_orange_pins: leds_orange_test-0 {
++ pins {
++ pinmux = <STM32_PINMUX('H', 7, GPIO)>;
++ bias-pull-up;
++ drive-push-pull;
++ output-low;
++ slew-rate = <0>;
++ };
++ };
++
++ leds_orange_sleep_pins: leds_orange_sleep_test-0 {
++ pins {
++ pinmux = <STM32_PINMUX('H', 7, ANALOG)>;
++ };
++ };
++};
++
++&timers1 {
++ status = "disabled";
++};
+diff --git a/arch/arm/boot/dts/phycore-stm32mp1-1.dts b/arch/arm/boot/dts/phycore-stm32mp1-1.dts
+new file mode 100644
+index 0000000..44d113a
+--- /dev/null
++++ b/arch/arm/boot/dts/phycore-stm32mp1-1.dts
+@@ -0,0 +1,15 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++/dts-v1/;
++
++#include "phycore-stm32mp1-1.dtsi"
++
++/ {
++ model = "Phytec GmbH phycore-stm32mp1-1 Dev Board";
++ compatible = "phycore-stm32mp1-1", "phytec,pcm939-1517-1-002", "st,stm32mp157";
++
++};
+diff --git a/arch/arm/boot/dts/phycore-stm32mp1-1.dtsi b/arch/arm/boot/dts/phycore-stm32mp1-1.dtsi
+new file mode 100644
+index 0000000..cb859bf
+--- /dev/null
++++ b/arch/arm/boot/dts/phycore-stm32mp1-1.dtsi
+@@ -0,0 +1,414 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++/dts-v1/;
++
++#include "phycore-stm32mp157cac-som.dtsi"
++#include <dt-bindings/leds/leds-pca9532.h>
++
++/ {
++ model = "Phytec GmbH phycore-stm32mp1-1 Dev Board";
++ compatible = "phytec,pcm939-1517-1-002", "st,stm32mp157";
++
++ aliases {
++ ethernet0 = &ethernet0;
++ rtc0 = &i2c4_rtc;
++ rtc1 = &rtc;
++ serial0 = &uart4;
++ serial1 = &uart7;
++ serial2 = &usart1;
++ serial3 = &usart3;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ sound {
++ compatible = "audio-graph-card";
++ label = "STM32MP1-PHYCORE";
++ routing =
++ "Playback", "MCLK", /* Set a route between "MCLK" and "playback" widgets */
++ "Capture", "MCLK";
++ dais = <&sai2b_port &sai2a_port>;
++ status = "okay";
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ status = "okay";
++
++ home {
++ label = "Home";
++ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_HOME>;
++ };
++
++ enter {
++ label = "Enter";
++ gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_ENTER>;
++ };
++ };
++
++ usb_phy_tuning: usb-phy-tuning {
++ st,hs-dc-level = <2>;
++ st,fs-rftime-tuning;
++ st,hs-rftime-reduction;
++ st,hs-current-trim = <15>;
++ st,hs-impedance-trim = <1>;
++ st,squelch-level = <3>;
++ st,hs-rx-offset = <2>;
++ st,no-lsfs-sc;
++ };
++
++ reg_m_can1: regulator-mcan1 {
++ compatible = "regulator-fixed";
++ regulator-name = "mcan1-reg";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpiog 1 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++ };
++};
++
++&m_can1 {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&m_can1_pins_a>;
++ pinctrl-1 = <&m_can1_sleep_pins_a>;
++ xceiver-supply = <&reg_m_can1>;
++ status = "okay";
++};
++
++&i2c1 {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&i2c1_pins_a>;
++ pinctrl-1 = <&i2c1_pins_sleep_a>;
++ i2c-scl-rising-time-ns = <100>;
++ i2c-scl-falling-time-ns = <7>;
++ status = "okay";
++ /delete-property/dmas;
++ /delete-property/dma-names;
++
++ codec: tlv320@18 {
++ compatible = "ti,tlv320aic3007";
++ #sound-dai-cells = <0>;
++ reg = <0x18>;
++ status = "okay";
++
++ ai3x-micbias-vg = <2>;
++
++ /* gpio-reset = <&gpio5 8 GPIO_ACTIVE_LOW>; */
++ AVDD-supply = <&v3v3>;
++ IOVDD-supply = <&v3v3>;
++ DRVDD-supply = <&v3v3>;
++ DVDD-supply = <&v1v8_audio>;
++
++ clocks = <&sai2b>;
++ clock-names = "MCLK";
++
++
++
++ tlv320_port: port {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ tlv320_tx_endpoint: endpoint@0 {
++ reg = <0>;
++ remote-endpoint = <&sai2b_endpoint>;
++ frame-master;
++ bitclock-master;
++ };
++
++ tlv320_rx_endpoint: endpoint@1 {
++ reg = <1>;
++ remote-endpoint = <&sai2a_endpoint>;
++ frame-master;
++ bitclock-master;
++ };
++ };
++ };
++
++ stmpe_touch: stmpe811@44 {
++ compatible = "st,stmpe811";
++ reg = <0x44>;
++ interrupts = <3 2>;
++ interrupt-parent = <&gpioi>;
++ vio-supply = <&v3v3>;
++ vcc-supply = <&v3v3>;
++ status = "disabled";
++
++ stmpe_touchscreen {
++ compatible = "st,stmpe-ts";
++ st,sample-time = <4>;
++ st,mod-12b = <1>;
++ st,ref-sel = <0>;
++ st,adc-freq = <1>;
++ st,ave-ctrl = <1>;
++ st,touch-det-delay = <2>;
++ st,settling = <2>;
++ st,fraction-z = <7>;
++ st,i-drive = <1>;
++ };
++ };
++
++ leds: pca9533@62 {
++ compatible = "nxp,pca9533";
++ reg = <0x62>;
++ status = "okay";
++
++ red-power {
++ label = "pca:red:power";
++ type = <PCA9532_TYPE_LED>;
++ };
++
++ green-power {
++ label = "pca:green:power";
++ type = <PCA9532_TYPE_LED>;
++ };
++
++ blue-power {
++ type = <PCA9532_TYPE_LED>;
++ linux,default-trigger = "heartbeat";
++ };
++ };
++};
++
++&i2c2 {
++ status = "disabled";
++};
++
++&i2s2 {
++ clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
++ clock-names = "pclk", "i2sclk", "x8k", "x11k";
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&i2s2_pins_a>;
++ pinctrl-1 = <&i2s2_pins_sleep_a>;
++ status = "disabled";
++
++ i2s2_port: port {
++ };
++};
++
++&sai2 {
++ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
++ clock-names = "pclk", "x8k", "x11k";
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&sai2a_pins_b>, <&sai2b_pins_a>;
++ pinctrl-1 = <&sai2a_sleep_pins_b>, <&sai2b_sleep_pins_a>;
++ status = "okay";
++
++ sai2a: audio-controller@4400b004 {
++ dma-names = "rx";
++ st,sync = <&sai2b 2>;
++ status = "okay";
++ clocks = <&rcc SAI2_K>, <&sai2b>;
++ clock-names = "sai_ck", "MCLK";
++
++ sai2a_port: port {
++ sai2a_endpoint: endpoint {
++ remote-endpoint = <&tlv320_rx_endpoint>;
++ format = "i2s";
++ mclk-fs = <256>;
++ dai-tdm-slot-num = <2>;
++ dai-tdm-slot-width = <16>;
++ };
++ };
++ };
++
++ sai2b: audio-controller@4400b024 {
++ #clock-cells = <0>;
++ dma-names = "tx";
++ clocks = <&rcc SAI2_K>;
++ clock-names = "sai_ck";
++ status = "okay";
++
++ sai2b_port: port {
++ sai2b_endpoint: endpoint {
++ remote-endpoint = <&tlv320_tx_endpoint>;
++ format = "i2s";
++ mclk-fs = <256>;
++ dai-tdm-slot-num = <2>;
++ dai-tdm-slot-width = <16>;
++ };
++ };
++ };
++};
++
++&sdmmc1 {
++ pinctrl-names = "default", "opendrain", "sleep";
++ pinctrl-0 = <&sdmmc1_b4_pins_a>;
++ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
++ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
++ cd-gpios = <&gpiof 3 GPIO_ACTIVE_LOW>;
++ st,neg-edge;
++ bus-width = <4>;
++ max-frequency = <10000000>;
++ vmmc-supply = <&v3v3>;
++ status = "okay";
++};
++
++&spi4 {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&spi4_pins_a>;
++ pinctrl-1 = <&spi4_sleep_pins_a>;
++ status = "disabled";
++};
++
++&spi5 {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&spi5_pins_a>;
++ pinctrl-1 = <&spi5_sleep_pins_a>;
++ status = "disabled";
++};
++
++&timers1 {
++ /* spare dmas for other usage */
++ /delete-property/dmas;
++ /delete-property/dma-names;
++ pwm {
++ pinctrl-0 = <&pwm1_pins_a>;
++ pinctrl-1 = <&pwm1_sleep_pins_a>;
++ pinctrl-names = "default", "sleep";
++ status = "disabled";
++ };
++ timer@0 {
++ status = "disabled";
++ };
++};
++
++&timers3 {
++ /delete-property/dmas;
++ /delete-property/dma-names;
++ pwm {
++ pinctrl-0 = <&pwm3_pins_a>;
++ pinctrl-1 = <&pwm3_sleep_pins_a>;
++ pinctrl-names = "default", "sleep";
++ status = "disabled";
++ };
++ timer@2 {
++ status = "disabled";
++ };
++};
++
++&timers4 {
++ /delete-property/dmas;
++ /delete-property/dma-names;
++ pwm {
++ pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>;
++ pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>;
++ pinctrl-names = "default", "sleep";
++ status = "disabled";
++ };
++ timer@3 {
++ status = "disabled";
++ };
++};
++
++&timers5 {
++ /delete-property/dmas;
++ /delete-property/dma-names;
++ pwm {
++ pinctrl-0 = <&pwm5_pins_a>;
++ pinctrl-1 = <&pwm5_sleep_pins_a>;
++ pinctrl-names = "default", "sleep";
++ status = "disabled";
++ };
++ timer@4 {
++ status = "disabled";
++ };
++};
++
++&timers6 {
++ status = "okay";
++ /* spare dmas for other usage */
++ /delete-property/dmas;
++ /delete-property/dma-names;
++ timer@5 {
++ status = "disabled";
++ };
++};
++
++&uart4 {
++ pinctrl-names = "default", "sleep", "idle", "no_console_suspend";
++ pinctrl-0 = <&uart4_pins_a>;
++ pinctrl-1 = <&uart4_sleep_pins_a>;
++ pinctrl-2 = <&uart4_idle_pins_a>;
++ pinctrl-3 = <&uart4_pins_a>;
++ status = "okay";
++};
++
++&uart7 {
++ pinctrl-names = "default", "sleep", "idle";
++ pinctrl-0 = <&uart7_pins_a>;
++ pinctrl-1 = <&uart7_sleep_pins_a>;
++ pinctrl-2 = <&uart7_idle_pins_a>;
++ status = "okay";
++};
++
++&usart1 {
++ pinctrl-names = "default", "sleep", "idle";
++ pinctrl-0 = <&usart1_pins_a>;
++ pinctrl-1 = <&usart1_sleep_pins_a>;
++ pinctrl-2 = <&usart1_idle_pins_a>;
++ status = "okay";
++};
++
++&usart3 {
++ pinctrl-names = "default", "sleep", "idle";
++ pinctrl-0 = <&usart3_pins_b>;
++ pinctrl-1 = <&usart3_sleep_pins_b>;
++ pinctrl-2 = <&usart3_idle_pins_b>;
++ st,hw-flow-ctrl;
++ status = "okay";
++};
++
++&usbh_ehci {
++ phys = <&usbphyc_port0>;
++ phy-names = "usb";
++ status = "okay";
++ vbus-supply = <&vbus_sw>;
++};
++
++&usbotg_hs {
++ force-b-session-valid;
++ phys = <&usbphyc_port1 0>;
++ phy-names = "usb2-phy";
++ vbus-supply = <&vbus_otg>;
++ status = "okay";
++};
++
++&usbphyc {
++ vdd3v3-supply = <&vdd_usb>;
++ status = "okay";
++};
++
++&usbphyc_port0 {
++ st,phy-tuning = <&usb_phy_tuning>;
++};
++
++&usbphyc_port1 {
++ st,phy-tuning = <&usb_phy_tuning>;
++};
++
++&vrefbuf {
++ regulator-min-microvolt = <2500000>;
++ regulator-max-microvolt = <2500000>;
++ vdda-supply = <&vdd>;
++ status = "disabled";
++};
++
++/* Select display interface by commenting/uncommenting the following lines */
++//#include "phycore-stm32mp1-dsi-lcd-mb1407.dtsi"
++//#include "phycore-stm32mp1-peb-av01-hdmi.dtsi"
++#include "phycore-stm32mp1-peb-av02-lcd.dtsi"
++
++
++/* Selected connectors used commenting/uncommenting the following line */
++//#include "phycore-stm32mp1-pi-hat-extension.dtsi"
++//#include "phycore-stm32mp1-uno-r3-extension.dtsi"
++//#include "phycore-stm32mp1-motor-control.dtsi"
++
+diff --git a/arch/arm/boot/dts/phycore-stm32mp1-dsi-lcd-mb1407.dtsi b/arch/arm/boot/dts/phycore-stm32mp1-dsi-lcd-mb1407.dtsi
+new file mode 100644
+index 0000000..2c872c9
+--- /dev/null
++++ b/arch/arm/boot/dts/phycore-stm32mp1-dsi-lcd-mb1407.dtsi
+@@ -0,0 +1,84 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++
++&i2c1 {
++ status = "okay";
++ touchscreen@2a {
++ compatible = "focaltech,ft6236";
++ reg = <0x2a>;
++ interrupts = <8 2>;
++ interrupt-parent = <&gpioi>;
++ interrupt-controller;
++ touchscreen-size-x = <480>;
++ touchscreen-size-y = <800>;
++ status = "okay";
++ };
++
++ touchscreen@38 {
++ compatible = "focaltech,ft6336";
++ reg = <0x38>;
++ interrupts = <8 2>;
++ interrupt-parent = <&gpioi>;
++ interrupt-controller;
++ touchscreen-size-x = <480>;
++ touchscreen-size-y = <800>;
++ status = "okay";
++ };
++}
++
++&ltdc {
++ dma-ranges;
++ status = "okay";
++
++ port {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ltdc_ep1_out: endpoint@1 {
++ reg = <1>;
++ remote-endpoint = <&dsi_in>;
++ };
++ };
++};
++
++&dsi {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ dsi_in: endpoint {
++ remote-endpoint = <&ltdc_ep1_out>;
++ };
++ };
++
++ port@1 {
++ reg = <1>;
++ dsi_out: endpoint {
++ remote-endpoint = <&panel_in>;
++ };
++ };
++ };
++
++ dsi_panel:panel@0 {
++ compatible = "orisetech,otm8009a";
++ reg = <0>;
++ reset-gpios = <&gpiod 9 GPIO_ACTIVE_LOW>;
++ status = "okay";
++
++ port {
++ panel_in: endpoint {
++ remote-endpoint = <&dsi_out>;
++ };
++ };
++ };
++};
+diff --git a/arch/arm/boot/dts/phycore-stm32mp1-motor-control.dtsi b/arch/arm/boot/dts/phycore-stm32mp1-motor-control.dtsi
+new file mode 100644
+index 0000000..cf2c3d1
+--- /dev/null
++++ b/arch/arm/boot/dts/phycore-stm32mp1-motor-control.dtsi
+@@ -0,0 +1,6 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
+diff --git a/arch/arm/boot/dts/phycore-stm32mp1-peb-av01-hdmi.dtsi b/arch/arm/boot/dts/phycore-stm32mp1-peb-av01-hdmi.dtsi
+new file mode 100644
+index 0000000..391d343
+--- /dev/null
++++ b/arch/arm/boot/dts/phycore-stm32mp1-peb-av01-hdmi.dtsi
+@@ -0,0 +1,43 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++&i2c1 {
++ tda19988@70 {
++ compatible = "nxp,tda998x";
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&ltdc_pins_a>;
++ pinctrl-1 = <&ltdc_pins_sleep_a>;
++ reg = <0x70>;
++ status = "okay";
++
++ ports {
++ port@0 {
++ hdmi_in: endpoint@0 {
++ remote-endpoint = <&ltdc_ep0_out>;
++ };
++ };
++ };
++ };
++};
++
++&ltdc {
++ dma-ranges;
++ status = "okay";
++
++ port {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ltdc_ep0_out: endpoint@0 {
++ reg = <0>;
++ remote-endpoint = <&hdmi_in>;
++ };
++ };
++};
++
++&dsi {
++ status = "disabled";
++};
+diff --git a/arch/arm/boot/dts/phycore-stm32mp1-peb-av02-lcd-res.dtsi b/arch/arm/boot/dts/phycore-stm32mp1-peb-av02-lcd-res.dtsi
+new file mode 100644
+index 0000000..077c215
+--- /dev/null
++++ b/arch/arm/boot/dts/phycore-stm32mp1-peb-av02-lcd-res.dtsi
+@@ -0,0 +1,76 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++/ {
++ panel_rgb: panel {
++ compatible = "edt,etm0700g0edh6";
++
++ status = "okay";
++ backlight = <&panel_backlight>;
++ enable-gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>;
++
++ port {
++ panel_in_rgb: endpoint {
++ remote-endpoint = <&ltdc_ep0_out>;
++ };
++ };
++ };
++
++ panel_backlight: panel-backlight {
++ compatible = "pwm-backlight";
++ pwms = <&pwm_5 3 100000>;
++
++ power-supply = <&v3v3>;
++
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <6>;
++ status = "okay";
++ };
++};
++
++&timers5 {
++ status = "okay";
++ /delete-property/dmas;
++ /delete-property/dma-names;
++ pwm_5: pwm {
++ #pwm-cells = <2>;
++ pinctrl-0 = <&pwm5_pins_a>;
++ pinctrl-1 = <&pwm5_sleep_pins_a>;
++ pinctrl-names = "default", "sleep";
++ status = "okay";
++ };
++
++ timer@4 {
++ status = "disabled";
++ };
++};
++
++&ltdc {
++ dma-ranges;
++ status = "okay";
++
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&ltdc_pins_a>;
++ pinctrl-1 = <&ltdc_pins_sleep_a>;
++
++ port {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ltdc_ep0_out: endpoint@0 {
++ reg = <0>;
++ remote-endpoint = <&panel_in_rgb>;
++ };
++ };
++};
++
++&stmpe_touch {
++ status = "okay";
++};
++
++&dsi {
++ status = "disabled";
++};
+diff --git a/arch/arm/boot/dts/phycore-stm32mp1-peb-av02-lcd.dtsi b/arch/arm/boot/dts/phycore-stm32mp1-peb-av02-lcd.dtsi
+new file mode 100644
+index 0000000..a24ebb4
+--- /dev/null
++++ b/arch/arm/boot/dts/phycore-stm32mp1-peb-av02-lcd.dtsi
+@@ -0,0 +1,83 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++/ {
++ panel_rgb: panel {
++ compatible = "edt,etm0700g0edh6";
++
++ status = "okay";
++ backlight = <&panel_backlight>;
++ enable-gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>;
++
++ port {
++ panel_in_rgb: endpoint {
++ remote-endpoint = <&ltdc_ep0_out>;
++ };
++ };
++ };
++
++ panel_backlight: panel-backlight {
++ compatible = "pwm-backlight";
++ pwms = <&pwm_5 3 100000>;
++
++ power-supply = <&v3v3>;
++
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <6>;
++ status = "okay";
++ };
++};
++
++&timers5 {
++ status = "okay";
++ /delete-property/dmas;
++ /delete-property/dma-names;
++ pwm_5: pwm {
++ #pwm-cells = <2>;
++ pinctrl-0 = <&pwm5_pins_a>;
++ pinctrl-1 = <&pwm5_sleep_pins_a>;
++ pinctrl-names = "default", "sleep";
++ status = "okay";
++ };
++
++ timer@4 {
++ status = "disabled";
++ };
++};
++
++&ltdc {
++ dma-ranges;
++ status = "okay";
++
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&ltdc_pins_a>;
++ pinctrl-1 = <&ltdc_pins_sleep_a>;
++
++ port {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ltdc_ep0_out: endpoint@0 {
++ reg = <0>;
++ remote-endpoint = <&panel_in_rgb>;
++ };
++ };
++};
++
++&i2c1 {
++ i2c_ts: touchscreen@38 {
++ compatible = "edt,edt-ft5x06";
++ reg = <0x38>;
++ interrupts = <8 2>;
++ interrupt-parent = <&gpioi>;
++ interrupt-controller;
++ status = "okay";
++ };
++};
++
++&dsi {
++ status = "disabled";
++};
+diff --git a/arch/arm/boot/dts/phycore-stm32mp1-pi-hat-extension.dtsi b/arch/arm/boot/dts/phycore-stm32mp1-pi-hat-extension.dtsi
+new file mode 100644
+index 0000000..fd27e09
+--- /dev/null
++++ b/arch/arm/boot/dts/phycore-stm32mp1-pi-hat-extension.dtsi
+@@ -0,0 +1,42 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
++
++&spi1 {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&spi1_pins_a>;
++ pinctrl-1 = <&spi1_sleep_pins_a>;
++ cs-gpios = <&gpiog 2 0>;
++ status = "okay";
++
++ spi@0 {
++ compatible = "spidev";
++ spi-max-frequency = <10000000>;
++ reg = <0>;
++ };
++};
++
++&sdmmc1 {
++ pinctrl-names = "default", "opendrain", "sleep";
++ pinctrl-0 = <&sdmmc1_b4_pins_a>;
++ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
++ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
++ cd-gpios = <&gpiof 3 GPIO_ACTIVE_LOW>;
++ st,neg-edge;
++ bus-width = <4>;
++ max-frequency = <10000000>;
++ vmmc-supply = <&v3v3>;
++ status = "disabled";
++};
++
++&i2c1 {
++ status = "okay";
++};
++
++&usart1 {
++ status = "okay";
++};
++
+diff --git a/arch/arm/boot/dts/phycore-stm32mp1-uno-r3-extension.dtsi b/arch/arm/boot/dts/phycore-stm32mp1-uno-r3-extension.dtsi
+new file mode 100644
+index 0000000..cf2c3d1
+--- /dev/null
++++ b/arch/arm/boot/dts/phycore-stm32mp1-uno-r3-extension.dtsi
+@@ -0,0 +1,6 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) PHYTEC GmbH 2019 - All Rights Reserved
++ * Author: Dom VOVARD <dom.vovard@linrt.com>.
++ */
++
+diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
+index 5581a1c..3e14a34 100644
+--- a/arch/arm/boot/dts/stm32mp157c.dtsi
++++ b/arch/arm/boot/dts/stm32mp157c.dtsi
+@@ -1749,10 +1749,14 @@
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
++ "eth-ck",
++ "syscfg-clk",
+ "ethstp";
+ clocks = <&rcc ETHMAC>,
+ <&rcc ETHTX>,
+ <&rcc ETHRX>,
++ <&rcc ETHCK_K>,
++ <&rcc SYSCFG>,
+ <&rcc ETHSTP>;
+ st,syscon = <&syscfg 0x4>;
+ snps,mixed-burst;
+diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
+index 97964f7..2818c9f 100644
+--- a/drivers/gpu/drm/panel/panel-simple.c
++++ b/drivers/gpu/drm/panel/panel-simple.c
+@@ -310,7 +310,7 @@ static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
+ return PTR_ERR(panel->supply);
+
+ panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
+- GPIOD_OUT_LOW);
++ GPIOD_OUT_HIGH);
+ if (IS_ERR(panel->enable_gpio)) {
+ err = PTR_ERR(panel->enable_gpio);
+ if (err != -EPROBE_DEFER)
+diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
+index f028277..d77e73b 100644
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -1072,6 +1072,7 @@ static const struct flash_info spi_nor_ids[] = {
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
++ { "is25lq128", INFO(0x9d6018, 0, 64 * 1024, 256, 0) },
+
+ /* Macronix */
+ { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
+@@ -1242,6 +1243,7 @@ static const struct flash_info spi_nor_ids[] = {
+ { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
+ { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
+ { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
++ { "w25q128", INFO(0xef7018, 0, 64 * 1024, 256, SECT_4K) },
+ { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
+ SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
+diff --git a/drivers/net/can/dev.c b/drivers/net/can/dev.c
+index 3b3f88f..4af7ce2 100644
+--- a/drivers/net/can/dev.c
++++ b/drivers/net/can/dev.c
+@@ -141,8 +141,10 @@ static int can_calc_bittiming(struct net_device *dev, struct can_bittiming *bt,
+ if (bt->sample_point) {
+ sample_point_nominal = bt->sample_point;
+ } else {
+- if (bt->bitrate > 800000)
++ if (bt->bitrate > 1000000)
+ sample_point_nominal = 750;
++ else if (bt->bitrate > 800000)
++ sample_point_nominal = 775;
+ else if (bt->bitrate > 500000)
+ sample_point_nominal = 800;
+ else
+diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
+index 9b44940..509935e 100644
+--- a/drivers/net/can/m_can/m_can.c
++++ b/drivers/net/can/m_can/m_can.c
+@@ -27,6 +27,7 @@
+ #include <linux/iopoll.h>
+ #include <linux/can/dev.h>
+ #include <linux/pinctrl/consumer.h>
++#include <linux/regulator/consumer.h>
+
+ /* napi related */
+ #define M_CAN_NAPI_WEIGHT 64
+@@ -361,6 +362,7 @@ struct m_can_priv {
+ struct device *device;
+ struct clk *hclk;
+ struct clk *cclk;
++ struct regulator *reg_xceiver;
+ void __iomem *base;
+ u32 irqstatus;
+ int version;
+@@ -407,6 +409,23 @@ static inline bool m_can_tx_fifo_full(const struct m_can_priv *priv)
+ return !!(m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQF);
+ }
+
++static inline int m_can_transceiver_enable(const struct m_can_priv *priv)
++{
++ if (!priv->reg_xceiver)
++ return 0;
++
++ return regulator_enable(priv->reg_xceiver);
++}
++
++
++static inline int m_can_transceiver_disable(const struct m_can_priv *priv)
++{
++ if (!priv->reg_xceiver)
++ return 0;
++
++ return regulator_disable(priv->reg_xceiver);
++}
++
+ static inline void m_can_config_endisable(const struct m_can_priv *priv,
+ bool enable)
+ {
+@@ -1159,6 +1178,7 @@ static void m_can_chip_config(struct net_device *dev)
+
+ static void m_can_start(struct net_device *dev)
+ {
++ int err;
+ struct m_can_priv *priv = netdev_priv(dev);
+
+ /* basic m_can configuration */
+@@ -1166,6 +1186,9 @@ static void m_can_start(struct net_device *dev)
+
+ priv->can.state = CAN_STATE_ERROR_ACTIVE;
+
++ err = m_can_transceiver_enable(priv);
++ if (err)
++ netdev_err(dev, "Transceiver enable error: %d \n", err);
+ m_can_enable_all_interrupts(priv);
+ }
+
+@@ -1352,6 +1375,8 @@ static void m_can_stop(struct net_device *dev)
+ /* disable all interrupts */
+ m_can_disable_all_interrupts(priv);
+
++ /* disable transceiver */
++ m_can_transceiver_disable(priv);
+ /* set the state as STOPPED */
+ priv->can.state = CAN_STATE_STOPPED;
+ }
+@@ -1575,6 +1600,7 @@ static int m_can_plat_probe(struct platform_device *pdev)
+ struct net_device *dev;
+ struct m_can_priv *priv;
+ struct resource *res;
++ struct regulator *reg_xceiver;
+ void __iomem *addr;
+ void __iomem *mram_addr;
+ struct clk *hclk, *cclk;
+@@ -1585,6 +1611,12 @@ static int m_can_plat_probe(struct platform_device *pdev)
+
+ np = pdev->dev.of_node;
+
++ reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
++ if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
++ return -EPROBE_DEFER;
++ else if (IS_ERR(reg_xceiver))
++ reg_xceiver = NULL;
++
+ hclk = devm_clk_get(&pdev->dev, "hclk");
+ cclk = devm_clk_get(&pdev->dev, "cclk");
+
+@@ -1644,6 +1676,7 @@ static int m_can_plat_probe(struct platform_device *pdev)
+ priv->cclk = cclk;
+ priv->can.clock.freq = clk_get_rate(cclk);
+ priv->mram_base = mram_addr;
++ priv->reg_xceiver = reg_xceiver;
+
+ platform_set_drvdata(pdev, dev);
+ SET_NETDEV_DEV(dev, &pdev->dev);
+diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
+index b393577..ff82f1b 100644
+--- a/drivers/net/phy/dp83867.c
++++ b/drivers/net/phy/dp83867.c
+@@ -19,6 +19,7 @@
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/phy.h>
++#include <linux/delay.h>
+
+ #include <dt-bindings/net/ti-dp83867.h>
+
+@@ -41,6 +42,13 @@
+ #define DP83867_SW_RESET BIT(15)
+ #define DP83867_SW_RESTART BIT(14)
+
++
++#define MIN_PHY_SW_DELAY_RESET 10 /* in uS */
++#define MAX_PHY_SW_DELAY_RESET (2 * MIN_PHY_SW_DELAY_RESET) /* in uS */
++
++/* PHYCTRL bits */
++#define MII_DP83867_PHYCTRL_FORCE_LINK_GOOD BIT(10)
++
+ /* MICR Interrupt bits */
+ #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
+ #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
+@@ -75,6 +83,7 @@
+
+ #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
+ #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
++#define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
+ #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
+ #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
+
+@@ -262,38 +271,37 @@ static int dp83867_config_init(struct phy_device *phydev)
+ return ret;
+ }
+
+- if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
+- (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
+- val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
+
+- if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+- val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
++ val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
+
+- if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+- val |= DP83867_RGMII_TX_CLK_DELAY_EN;
++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
++ val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
+
+- if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+- val |= DP83867_RGMII_RX_CLK_DELAY_EN;
++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
++ val |= DP83867_RGMII_TX_CLK_DELAY_EN;
+
+- phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
++ val |= DP83867_RGMII_RX_CLK_DELAY_EN;
+
+- delay = (dp83867->rx_id_delay |
+- (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
++ phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
+
+- phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
+- delay);
+
+- if (dp83867->io_impedance >= 0) {
+- val = phy_read_mmd(phydev, DP83867_DEVADDR,
+- DP83867_IO_MUX_CFG);
+
+- val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
+- val |= dp83867->io_impedance &
+- DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
++ delay = (dp83867->rx_id_delay |
++ (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
+
+- phy_write_mmd(phydev, DP83867_DEVADDR,
++ phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
++ delay);
++
++ if (dp83867->io_impedance >= 0) {
++ val = phy_read_mmd(phydev, DP83867_DEVADDR,
++ DP83867_IO_MUX_CFG);
++
++ val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
++ val |= dp83867->io_impedance &
++ DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
++ phy_write_mmd(phydev, DP83867_DEVADDR,
+ DP83867_IO_MUX_CFG, val);
+- }
+ }
+
+ /* Enable Interrupt output INT_OE in CFG3 register */
+@@ -309,11 +317,25 @@ static int dp83867_config_init(struct phy_device *phydev)
+ /* Clock output selection if muxing property is set */
+ if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
+ val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG);
+- val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
+- val |= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
++
++ if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
++ val |= DP83867_IO_MUX_CFG_CLK_O_DISABLE;
++ } else {
++ val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
++ val |= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
++ }
++
+ phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val);
+ }
+
++ /* Disable FORCE_LINK_GOOD */
++ val = phy_read(phydev, MII_DP83867_PHYCTRL);
++
++ if (val & MII_DP83867_PHYCTRL_FORCE_LINK_GOOD) {
++ val &= ~(MII_DP83867_PHYCTRL_FORCE_LINK_GOOD);
++ phy_write(phydev, MII_DP83867_PHYCTRL, val);
++ }
++
+ return 0;
+ }
+
+@@ -325,6 +347,7 @@ static int dp83867_phy_reset(struct phy_device *phydev)
+ if (err < 0)
+ return err;
+
++ usleep_range(MIN_PHY_SW_DELAY_RESET, MAX_PHY_SW_DELAY_RESET);
+ return dp83867_config_init(phydev);
+ }
+
+diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
+index 6e201ff..4a6748d 100644
+--- a/drivers/rtc/Kconfig
++++ b/drivers/rtc/Kconfig
+@@ -625,6 +625,15 @@ config RTC_DRV_EM3027
+ This driver can also be built as a module. If so, the module
+ will be called rtc-em3027.
+
++config RTC_DRV_RV3028
++ tristate "Micro Crystal RV3028"
++ help
++ If you say yes here you get support for the Micro Crystal
++ RV3028.
++
++ This driver can also be built as a module. If so, the module
++ will be called rtc-rv3028.
++
+ config RTC_DRV_RV8803
+ tristate "Micro Crystal RV8803, Epson RX8900"
+ help
+diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
+index 5ff2fc0..7c1ec1c 100644
+--- a/drivers/rtc/Makefile
++++ b/drivers/rtc/Makefile
+@@ -136,6 +136,7 @@ obj-$(CONFIG_RTC_DRV_RS5C313) += rtc-rs5c313.o
+ obj-$(CONFIG_RTC_DRV_RS5C348) += rtc-rs5c348.o
+ obj-$(CONFIG_RTC_DRV_RS5C372) += rtc-rs5c372.o
+ obj-$(CONFIG_RTC_DRV_RTD119X) += rtc-rtd119x.o
++obj-$(CONFIG_RTC_DRV_RV3028) += rtc-rv3028.o
+ obj-$(CONFIG_RTC_DRV_RV3029C2) += rtc-rv3029c2.o
+ obj-$(CONFIG_RTC_DRV_RV8803) += rtc-rv8803.o
+ obj-$(CONFIG_RTC_DRV_RX4581) += rtc-rx4581.o
+diff --git a/drivers/rtc/rtc-rv3028.c b/drivers/rtc/rtc-rv3028.c
+new file mode 100644
+index 0000000..327316b
+--- /dev/null
++++ b/drivers/rtc/rtc-rv3028.c
+@@ -0,0 +1,750 @@
++//SPDX
++/*
++ * RTC driver for the Micro Crystal RV3028
++ *
++ * Copyright (C) 2018 Micro Crystal SA
++ *
++ * Alexandre Belloni <alexandre.belloni@bootlin.com>
++ *
++ */
++
++#include <linux/bcd.h>
++#include <linux/bitops.h>
++#include <linux/i2c.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/log2.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/regmap.h>
++#include <linux/rtc.h>
++#include "rtc-core.h"
++
++
++#define RV3028_SEC 0x00
++#define RV3028_MIN 0x01
++#define RV3028_HOUR 0x02
++#define RV3028_WDAY 0x03
++#define RV3028_DAY 0x04
++#define RV3028_MONTH 0x05
++#define RV3028_YEAR 0x06
++#define RV3028_ALARM_MIN 0x07
++#define RV3028_ALARM_HOUR 0x08
++#define RV3028_ALARM_DAY 0x09
++#define RV3028_STATUS 0x0E
++#define RV3028_CTRL1 0x0F
++#define RV3028_CTRL2 0x10
++#define RV3028_EVT_CTRL 0x13
++#define RV3028_TS_COUNT 0x14
++#define RV3028_TS_SEC 0x15
++#define RV3028_RAM1 0x1F
++#define RV3028_EEPROM_ADDR 0x25
++#define RV3028_EEPROM_DATA 0x26
++#define RV3028_EEPROM_CMD 0x27
++#define RV3028_CLKOUT 0x35
++#define RV3028_OFFSET 0x36
++#define RV3028_BACKUP 0x37
++
++#define RV3028_STATUS_PORF BIT(0)
++#define RV3028_STATUS_EVF BIT(1)
++#define RV3028_STATUS_AF BIT(2)
++#define RV3028_STATUS_TF BIT(3)
++#define RV3028_STATUS_UF BIT(4)
++#define RV3028_STATUS_BSF BIT(5)
++#define RV3028_STATUS_CLKF BIT(6)
++#define RV3028_STATUS_EEBUSY BIT(7)
++
++#define RV3028_CTRL1_EERD BIT(3)
++#define RV3028_CTRL1_WADA BIT(5)
++
++#define RV3028_CTRL2_RESET BIT(0)
++#define RV3028_CTRL2_12_24 BIT(1)
++#define RV3028_CTRL2_EIE BIT(2)
++#define RV3028_CTRL2_AIE BIT(3)
++#define RV3028_CTRL2_TIE BIT(4)
++#define RV3028_CTRL2_UIE BIT(5)
++#define RV3028_CTRL2_TSE BIT(7)
++
++#define RV3028_EVT_CTRL_TSR BIT(2)
++
++#define RV3028_EEPROM_CMD_WRITE 0x21
++#define RV3028_EEPROM_CMD_READ 0x22
++
++#define RV3028_EEBUSY_POLL 10000
++#define RV3028_EEBUSY_TIMEOUT 100000
++
++#define RV3028_BACKUP_TCE BIT(5)
++#define RV3028_BACKUP_TCR_MASK GENMASK(1,0)
++#define RV3028_BACKUP_BSM_MASK 0x0c
++
++#define OFFSET_STEP_PPT 953674
++
++
++enum rv3028_type {
++ rv_3028,
++};
++
++struct rv3028_data {
++ struct regmap *regmap;
++ struct rtc_device *rtc;
++ enum rv3028_type type;
++};
++
++static u32 rv3028_trickle_resistors[] = {1000, 3000, 6000, 11000};
++
++static ssize_t timestamp0_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct rv3028_data *rv3028 = dev_get_drvdata(dev->parent);
++
++ regmap_update_bits(rv3028->regmap, RV3028_EVT_CTRL, RV3028_EVT_CTRL_TSR,
++ RV3028_EVT_CTRL_TSR);
++
++ return count;
++};
++
++static ssize_t timestamp0_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct rv3028_data *rv3028 = dev_get_drvdata(dev->parent);
++ struct rtc_time tm;
++ int ret, count;
++ u8 date[6];
++
++ ret = regmap_read(rv3028->regmap, RV3028_TS_COUNT, &count);
++ if (ret)
++ return ret;
++
++ if (!count)
++ return 0;
++
++ ret = regmap_bulk_read(rv3028->regmap, RV3028_TS_SEC, date,
++ sizeof(date));
++ if (ret)
++ return ret;
++
++ tm.tm_sec = bcd2bin(date[0]);
++ tm.tm_min = bcd2bin(date[1]);
++ tm.tm_hour = bcd2bin(date[2]);
++ tm.tm_mday = bcd2bin(date[3]);
++ tm.tm_mon = bcd2bin(date[4]) - 1;
++ tm.tm_year = bcd2bin(date[5]) + 100;
++
++ ret = rtc_valid_tm(&tm);
++ if (ret)
++ return ret;
++
++ return sprintf(buf, "%llu\n",
++ (unsigned long long)rtc_tm_to_time64(&tm));
++};
++
++static DEVICE_ATTR_RW(timestamp0);
++
++static ssize_t timestamp0_count_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct rv3028_data *rv3028 = dev_get_drvdata(dev->parent);
++ int ret, count;
++
++ ret = regmap_read(rv3028->regmap, RV3028_TS_COUNT, &count);
++ if (ret)
++ return ret;
++
++ return sprintf(buf, "%u\n", count);
++};
++
++static DEVICE_ATTR_RO(timestamp0_count);
++
++static struct attribute *rv3028_attrs[] = {
++ &dev_attr_timestamp0.attr,
++ &dev_attr_timestamp0_count.attr,
++ NULL
++};
++
++static const struct attribute_group rv3028_attr_group = {
++ .attrs = rv3028_attrs,
++};
++
++static irqreturn_t rv3028_handle_irq(int irq, void *dev_id)
++{
++ struct rv3028_data *rv3028 = dev_id;
++ unsigned long events = 0;
++ u32 status = 0, ctrl = 0;
++
++ if (regmap_read(rv3028->regmap, RV3028_STATUS, &status) < 0 ||
++ status == 0) {
++ return IRQ_NONE;
++ }
++
++ if (status & RV3028_STATUS_PORF)
++ dev_warn(&rv3028->rtc->dev, "Voltage low, data loss detected.\n");
++
++ if (status & RV3028_STATUS_TF) {
++ status |= RV3028_STATUS_TF;
++ ctrl |= RV3028_CTRL2_TIE;
++ events |= RTC_PF;
++ }
++
++ if (status & RV3028_STATUS_AF) {
++ status |= RV3028_STATUS_AF;
++ ctrl |= RV3028_CTRL2_AIE;
++ events |= RTC_AF;
++ }
++
++ if (status & RV3028_STATUS_UF) {
++ status |= RV3028_STATUS_UF;
++ ctrl |= RV3028_CTRL2_UIE;
++ events |= RTC_UF;
++ }
++
++ if (events) {
++ rtc_update_irq(rv3028->rtc, 1, events);
++ regmap_update_bits(rv3028->regmap, RV3028_STATUS, status, 0);
++ regmap_update_bits(rv3028->regmap, RV3028_CTRL2, ctrl, 0);
++ }
++
++ if (status & RV3028_STATUS_EVF) {
++ sysfs_notify(&rv3028->rtc->dev.kobj, NULL,
++ dev_attr_timestamp0.attr.name);
++ dev_warn(&rv3028->rtc->dev, "event detected");
++ }
++
++ return IRQ_HANDLED;
++}
++
++static int rv3028_get_time(struct device *dev, struct rtc_time *tm)
++{
++ struct rv3028_data *rv3028 = dev_get_drvdata(dev);
++ u8 date[7];
++ int ret, status;
++
++ ret = regmap_read(rv3028->regmap, RV3028_STATUS, &status);
++ if (ret < 0)
++ return ret;
++
++ if (status & RV3028_STATUS_PORF) {
++ dev_warn(dev, "Voltage low, data is invalid.\n");
++ return -EINVAL;
++ }
++
++ ret = regmap_bulk_read(rv3028->regmap, RV3028_SEC, date, sizeof(date));
++ if (ret)
++ return ret;
++
++ tm->tm_sec = bcd2bin(date[RV3028_SEC] & 0x7f);
++ tm->tm_min = bcd2bin(date[RV3028_MIN] & 0x7f);
++ tm->tm_hour = bcd2bin(date[RV3028_HOUR] & 0x3f);
++ tm->tm_wday = ilog2(date[RV3028_WDAY] & 0x7f);
++ tm->tm_mday = bcd2bin(date[RV3028_DAY] & 0x3f);
++ tm->tm_mon = bcd2bin(date[RV3028_MONTH] & 0x1f) - 1;
++ tm->tm_year = bcd2bin(date[RV3028_YEAR]) + 100;
++
++ return 0;
++}
++
++static int rv3028_set_time(struct device *dev, struct rtc_time *tm)
++{
++ struct rv3028_data *rv3028 = dev_get_drvdata(dev);
++ u8 date[7];
++ int ret;
++
++ date[RV3028_SEC] = bin2bcd(tm->tm_sec);
++ date[RV3028_MIN] = bin2bcd(tm->tm_min);
++ date[RV3028_HOUR] = bin2bcd(tm->tm_hour);
++ date[RV3028_WDAY] = 1 << (tm->tm_wday);
++ date[RV3028_DAY] = bin2bcd(tm->tm_mday);
++ date[RV3028_MONTH] = bin2bcd(tm->tm_mon + 1);
++ date[RV3028_YEAR] = bin2bcd(tm->tm_year - 100);
++
++ /*
++ * Writing to the Seconds register has the same effect as setting RESET
++ * bit to 1
++ */
++ ret = regmap_bulk_write(rv3028->regmap, RV3028_SEC, date,
++ sizeof(date));
++ if (ret)
++ return ret;
++
++ ret = regmap_update_bits(rv3028->regmap, RV3028_STATUS,
++ RV3028_STATUS_PORF, 0);
++
++ return ret;
++}
++
++static int rv3028_get_alarm(struct device *dev, struct rtc_wkalrm *alrm)
++{
++ struct rv3028_data *rv3028 = dev_get_drvdata(dev);
++ u8 alarmvals[3];
++ int status, ctrl, ret;
++
++ ret = regmap_bulk_read(rv3028->regmap, RV3028_ALARM_MIN, alarmvals,
++ sizeof(alarmvals));
++ if (ret)
++ return ret;
++
++ ret = regmap_read(rv3028->regmap, RV3028_STATUS, &status);
++ if (ret < 0)
++ return ret;
++
++ ret = regmap_read(rv3028->regmap, RV3028_CTRL2, &ctrl);
++ if (ret < 0)
++ return ret;
++
++ alrm->time.tm_sec = 0;
++ alrm->time.tm_min = bcd2bin(alarmvals[0] & 0x7f);
++ alrm->time.tm_hour = bcd2bin(alarmvals[1] & 0x3f);
++ alrm->time.tm_mday = bcd2bin(alarmvals[2] & 0x3f);
++
++ alrm->enabled = !!(ctrl & RV3028_CTRL2_AIE);
++ alrm->pending = (status & RV3028_STATUS_AF) && alrm->enabled;
++
++ return 0;
++}
++
++static int rv3028_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
++{
++ struct rv3028_data *rv3028 = dev_get_drvdata(dev);
++ u8 alarmvals[3];
++ u8 ctrl = 0;
++ int ret;
++
++ /* The alarm has no seconds, round up to nearest minute */
++ if (alrm->time.tm_sec) {
++ time64_t alarm_time = rtc_tm_to_time64(&alrm->time);
++
++ alarm_time += 60 - alrm->time.tm_sec;
++ rtc_time64_to_tm(alarm_time, &alrm->time);
++ }
++
++ ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL2,
++ RV3028_CTRL2_AIE | RV3028_CTRL2_UIE, 0);
++ if (ret)
++ return ret;
++
++ alarmvals[0] = bin2bcd(alrm->time.tm_min);
++ alarmvals[1] = bin2bcd(alrm->time.tm_hour);
++ alarmvals[2] = bin2bcd(alrm->time.tm_mday);
++
++ ret = regmap_update_bits(rv3028->regmap, RV3028_STATUS,
++ RV3028_STATUS_AF, 0);
++ if (ret)
++ return ret;
++
++ ret = regmap_bulk_write(rv3028->regmap, RV3028_ALARM_MIN, alarmvals,
++ sizeof(alarmvals));
++ if (ret)
++ return ret;
++
++ if (alrm->enabled) {
++ if (rv3028->rtc->uie_rtctimer.enabled)
++ ctrl |= RV3028_CTRL2_UIE;
++ if (rv3028->rtc->aie_timer.enabled)
++ ctrl |= RV3028_CTRL2_AIE;
++ }
++
++ ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL2,
++ RV3028_CTRL2_UIE | RV3028_CTRL2_AIE, ctrl);
++
++ return ret;
++}
++
++static int rv3028_alarm_irq_enable(struct device *dev, unsigned int enabled)
++{
++ struct rv3028_data *rv3028 = dev_get_drvdata(dev);
++ int ctrl = 0, ret;
++
++ if (enabled) {
++ if (rv3028->rtc->uie_rtctimer.enabled)
++ ctrl |= RV3028_CTRL2_UIE;
++ if (rv3028->rtc->aie_timer.enabled)
++ ctrl |= RV3028_CTRL2_AIE;
++ }
++
++ ret = regmap_update_bits(rv3028->regmap, RV3028_STATUS,
++ RV3028_STATUS_AF | RV3028_STATUS_UF, 0);
++ if (ret)
++ return ret;
++
++ ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL2,
++ RV3028_CTRL2_UIE | RV3028_CTRL2_AIE, ctrl);
++ if (ret)
++ return ret;
++
++ return 0;
++}
++
++static int rv3028_read_offset(struct device *dev, long *offset)
++{
++ struct rv3028_data *rv3028 = dev_get_drvdata(dev);
++ int ret, value, steps;
++
++ ret = regmap_read(rv3028->regmap, RV3028_OFFSET, &value);
++ if (ret < 0)
++ return ret;
++
++ steps = sign_extend32(value << 1, 8);
++
++ ret = regmap_read(rv3028->regmap, RV3028_BACKUP, &value);
++ if (ret < 0)
++ return ret;
++
++ steps += value >> 7;
++
++ *offset = DIV_ROUND_CLOSEST(steps * OFFSET_STEP_PPT, 1000);
++
++ return 0;
++}
++
++static int rv3028_set_offset(struct device *dev, long offset)
++{
++ struct rv3028_data *rv3028 = dev_get_drvdata(dev);
++ int ret;
++
++ offset = clamp(offset, -244141L, 243187L) * 1000;
++ offset = DIV_ROUND_CLOSEST(offset, OFFSET_STEP_PPT);
++
++ ret = regmap_write(rv3028->regmap, RV3028_OFFSET, offset >> 1);
++ if (ret < 0)
++ return ret;
++
++ return regmap_update_bits(rv3028->regmap, RV3028_BACKUP, BIT(7),
++ offset << 7);
++}
++
++static int rv3028_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
++{
++ struct rv3028_data *rv3028 = dev_get_drvdata(dev);
++ int status, ret = 0;
++
++ switch (cmd) {
++ case RTC_VL_READ:
++ ret = regmap_read(rv3028->regmap, RV3028_STATUS, &status);
++ if (ret < 0)
++ return ret;
++
++ if (status & RV3028_STATUS_PORF)
++ dev_warn(&rv3028->rtc->dev, "Voltage low, data loss detected.\n");
++
++ status &= RV3028_STATUS_PORF;
++
++ if (copy_to_user((void __user *)arg, &status, sizeof(int)))
++ return -EFAULT;
++
++ return 0;
++
++ case RTC_VL_CLR:
++ ret = regmap_update_bits(rv3028->regmap, RV3028_STATUS,
++ RV3028_STATUS_PORF, 0);
++
++ return ret;
++
++ default:
++ return -ENOIOCTLCMD;
++ }
++}
++
++static int rv3028_nvram_write(void *priv, unsigned int offset, void *val,
++ size_t bytes)
++{
++ return regmap_bulk_write(priv, RV3028_RAM1 + offset, val, bytes);
++}
++
++static int rv3028_nvram_read(void *priv, unsigned int offset, void *val,
++ size_t bytes)
++{
++ return regmap_bulk_read(priv, RV3028_RAM1 + offset, val, bytes);
++}
++
++static int rv3028_eeprom_write(void *priv, unsigned int offset, void *val,
++ size_t bytes)
++{
++ u32 status, ctrl1;
++ int i, ret, err;
++ u8 *buf = val;
++
++ ret = regmap_read(priv, RV3028_CTRL1, &ctrl1);
++ if (ret)
++ return ret;
++
++ if (!(ctrl1 & RV3028_CTRL1_EERD)) {
++ ret = regmap_update_bits(priv, RV3028_CTRL1,
++ RV3028_CTRL1_EERD, RV3028_CTRL1_EERD);
++ if (ret)
++ return ret;
++
++ ret = regmap_read_poll_timeout(priv, RV3028_STATUS, status,
++ !(status & RV3028_STATUS_EEBUSY),
++ RV3028_EEBUSY_POLL,
++ RV3028_EEBUSY_TIMEOUT);
++ if (ret)
++ goto restore_eerd;
++ }
++
++ for (i = 0; i < bytes; i++) {
++ ret = regmap_write(priv, RV3028_EEPROM_ADDR, offset + i);
++ if (ret)
++ goto restore_eerd;
++
++ ret = regmap_write(priv, RV3028_EEPROM_DATA, buf[i]);
++ if (ret)
++ goto restore_eerd;
++
++ ret = regmap_write(priv, RV3028_EEPROM_CMD, 0x0);
++ if (ret)
++ goto restore_eerd;
++
++ ret = regmap_write(priv, RV3028_EEPROM_CMD,
++ RV3028_EEPROM_CMD_WRITE);
++ if (ret)
++ goto restore_eerd;
++
++ usleep_range(RV3028_EEBUSY_POLL, RV3028_EEBUSY_TIMEOUT);
++
++ ret = regmap_read_poll_timeout(priv, RV3028_STATUS, status,
++ !(status & RV3028_STATUS_EEBUSY),
++ RV3028_EEBUSY_POLL,
++ RV3028_EEBUSY_TIMEOUT);
++ if (ret)
++ goto restore_eerd;
++ }
++
++restore_eerd:
++ if (!(ctrl1 & RV3028_CTRL1_EERD))
++ {
++ err = regmap_update_bits(priv, RV3028_CTRL1, RV3028_CTRL1_EERD,
++ 0);
++ if (err && !ret)
++ ret = err;
++ }
++
++ return ret;
++}
++
++static int rv3028_eeprom_read(void *priv, unsigned int offset, void *val,
++ size_t bytes)
++{
++ u32 status, ctrl1, data;
++ int i, ret, err;
++ u8 *buf = val;
++
++ ret = regmap_read(priv, RV3028_CTRL1, &ctrl1);
++ if (ret)
++ return ret;
++
++ if (!(ctrl1 & RV3028_CTRL1_EERD)) {
++ ret = regmap_update_bits(priv, RV3028_CTRL1,
++ RV3028_CTRL1_EERD, RV3028_CTRL1_EERD);
++ if (ret)
++ return ret;
++
++ ret = regmap_read_poll_timeout(priv, RV3028_STATUS, status,
++ !(status & RV3028_STATUS_EEBUSY),
++ RV3028_EEBUSY_POLL,
++ RV3028_EEBUSY_TIMEOUT);
++ if (ret)
++ goto restore_eerd;
++ }
++
++ for (i = 0; i < bytes; i++) {
++ ret = regmap_write(priv, RV3028_EEPROM_ADDR, offset + i);
++ if (ret)
++ goto restore_eerd;
++
++ ret = regmap_write(priv, RV3028_EEPROM_CMD, 0x0);
++ if (ret)
++ goto restore_eerd;
++
++ ret = regmap_write(priv, RV3028_EEPROM_CMD,
++ RV3028_EEPROM_CMD_READ);
++ if (ret)
++ goto restore_eerd;
++
++ ret = regmap_read_poll_timeout(priv, RV3028_STATUS, status,
++ !(status & RV3028_STATUS_EEBUSY),
++ RV3028_EEBUSY_POLL,
++ RV3028_EEBUSY_TIMEOUT);
++ if (ret)
++ goto restore_eerd;
++
++ ret = regmap_read(priv, RV3028_EEPROM_DATA, &data);
++ if (ret)
++ goto restore_eerd;
++ buf[i] = data;
++ }
++
++restore_eerd:
++ if (!(ctrl1 & RV3028_CTRL1_EERD))
++ {
++ err = regmap_update_bits(priv, RV3028_CTRL1, RV3028_CTRL1_EERD,
++ 0);
++ if (err && !ret)
++ ret = err;
++ }
++
++ return ret;
++}
++
++static struct rtc_class_ops rv3028_rtc_ops = {
++ .read_time = rv3028_get_time,
++ .set_time = rv3028_set_time,
++ .read_offset = rv3028_read_offset,
++ .set_offset = rv3028_set_offset,
++ .ioctl = rv3028_ioctl,
++};
++
++static const struct regmap_config regmap_config = {
++ .reg_bits = 8,
++ .val_bits = 8,
++ .max_register = 0x37,
++};
++
++static int rv3028_probe(struct i2c_client *client)
++{
++ struct rv3028_data *rv3028;
++ int ret, status;
++ u32 ohms;
++ u8 bsm;
++ struct nvmem_config nvmem_cfg = {
++ .name = "rv3028_nvram",
++ .word_size = 1,
++ .stride = 1,
++ .size = 2,
++ .reg_read = rv3028_nvram_read,
++ .reg_write = rv3028_nvram_write,
++ };
++ struct nvmem_config eeprom_cfg = {
++ .name = "rv3028_eeprom",
++ .word_size = 1,
++ .stride = 1,
++ .size = 43,
++ .reg_read = rv3028_eeprom_read,
++ .reg_write = rv3028_eeprom_write,
++ };
++
++ rv3028 = devm_kzalloc(&client->dev, sizeof(struct rv3028_data),
++ GFP_KERNEL);
++ if (!rv3028)
++ return -ENOMEM;
++
++ rv3028->regmap = devm_regmap_init_i2c(client, &regmap_config);
++
++ i2c_set_clientdata(client, rv3028);
++
++ ret = regmap_read(rv3028->regmap, RV3028_STATUS, &status);
++ if (ret < 0)
++ return ret;
++
++ if (status & RV3028_STATUS_PORF)
++ dev_warn(&client->dev, "Voltage low, data loss detected.\n");
++
++ if (status & RV3028_STATUS_AF)
++ dev_warn(&client->dev, "An alarm may have been missed.\n");
++
++ rv3028->rtc = devm_rtc_allocate_device(&client->dev);
++ if (IS_ERR(rv3028->rtc)) {
++ return PTR_ERR(rv3028->rtc);
++ }
++
++ if (client->irq > 0) {
++ ret = devm_request_threaded_irq(&client->dev, client->irq,
++ NULL, rv3028_handle_irq,
++ IRQF_TRIGGER_LOW | IRQF_ONESHOT,
++ "rv3028", rv3028);
++ if (ret) {
++ dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n");
++ client->irq = 0;
++ } else {
++ rv3028_rtc_ops.read_alarm = rv3028_get_alarm;
++ rv3028_rtc_ops.set_alarm = rv3028_set_alarm;
++ rv3028_rtc_ops.alarm_irq_enable = rv3028_alarm_irq_enable;
++ }
++ }
++
++ ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL1,
++ RV3028_CTRL1_WADA, RV3028_CTRL1_WADA);
++ if (ret)
++ return ret;
++
++ /* setup timestamping */
++ ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL2,
++ RV3028_CTRL2_EIE | RV3028_CTRL2_TSE,
++ RV3028_CTRL2_EIE | RV3028_CTRL2_TSE);
++ if (ret)
++ return ret;
++
++ /* setup backup switchover mode */
++ if (!device_property_read_u8(&client->dev, "backup-switchover-mode",
++ &bsm)) {
++ if (bsm <= 3) {
++ ret = regmap_update_bits(rv3028->regmap, RV3028_BACKUP,
++ RV3028_BACKUP_BSM_MASK,
++ (bsm & 0x03) << 2);
++ if (ret)
++ return ret;
++ dev_info(&client->dev, "backup switchover mode : %d\n", bsm);
++
++ } else {
++ dev_warn(&client->dev, "invalid backup switchover mode value\n");
++ }
++ }
++
++ /* setup trickle charger */
++ if (!device_property_read_u32(&client->dev, "trickle-resistor-ohms",
++ &ohms)) {
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(rv3028_trickle_resistors); i++)
++ if (ohms == rv3028_trickle_resistors[i])
++ break;
++
++ if (i < ARRAY_SIZE(rv3028_trickle_resistors)) {
++ ret = regmap_update_bits(rv3028->regmap, RV3028_BACKUP,
++ RV3028_BACKUP_TCE |
++ RV3028_BACKUP_TCR_MASK,
++ RV3028_BACKUP_TCE | i);
++ if (ret)
++ return ret;
++ } else {
++ dev_warn(&client->dev, "invalid trickle resistor value\n");
++ }
++ }
++
++ ret = rtc_add_group(rv3028->rtc, &rv3028_attr_group);
++ if (ret)
++ return ret;
++
++ rv3028->rtc->range_max = RTC_TIMESTAMP_END_2099;
++ rv3028->rtc->ops = &rv3028_rtc_ops;
++ ret = rtc_register_device(rv3028->rtc);
++ if (ret)
++ return ret;
++
++ nvmem_cfg.priv = rv3028->regmap;
++ rtc_nvmem_register(rv3028->rtc, &nvmem_cfg);
++ eeprom_cfg.priv = rv3028->regmap;
++ rtc_nvmem_register(rv3028->rtc, &eeprom_cfg);
++
++ rv3028->rtc->max_user_freq = 1;
++
++ return 0;
++}
++
++static const struct of_device_id rv3028_of_match[] = {
++ { .compatible = "microcrystal,rv3028", },
++ { }
++};
++MODULE_DEVICE_TABLE(of, rv3028_of_match);
++
++static struct i2c_driver rv3028_driver = {
++ .driver = {
++ .name = "rtc-rv3028",
++ .of_match_table = of_match_ptr(rv3028_of_match),
++ },
++ .probe_new = rv3028_probe,
++};
++module_i2c_driver(rv3028_driver);
++
++MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
++MODULE_DESCRIPTION("Micro Crystal RV3028 RTC driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h
+index 7b16564..e1d0c24 100644
+--- a/include/dt-bindings/net/ti-dp83867.h
++++ b/include/dt-bindings/net/ti-dp83867.h
+@@ -56,4 +56,7 @@
+ #define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA
+ #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB
+ #define DP83867_CLK_O_SEL_REF_CLK 0xC
++
++/* Special flag to indicate clock should be off */
++#define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF
+ #endif
+diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
+index 6a271e6..f7f25b1 100644
+--- a/sound/soc/codecs/tlv320aic3x.c
++++ b/sound/soc/codecs/tlv320aic3x.c
+@@ -32,6 +32,7 @@
+ * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
+ */
+
++#include <linux/clk.h>
+ #include <linux/module.h>
+ #include <linux/moduleparam.h>
+ #include <linux/init.h>
+@@ -78,6 +79,7 @@ struct aic3x_priv {
+ struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
+ struct aic3x_setup_data *setup;
+ unsigned int sysclk;
++ struct clk *mclk_handle;
+ unsigned int dai_fmt;
+ unsigned int tdm_delay;
+ unsigned int slot_width;
+@@ -993,11 +995,23 @@ static const struct snd_soc_dapm_route intercon_3007[] = {
+ {"SPOM", NULL, "Right Class-D Out"},
+ };
+
++static const struct snd_soc_dapm_widget aic3x_dapm_mclk_widgets[] = {
++ SND_SOC_DAPM_CLOCK_SUPPLY("MCLK")
++};
++
+ static int aic3x_add_widgets(struct snd_soc_component *component)
+ {
+ struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
+ struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
+
++
++ if (aic3x->mclk_handle) {
++ snd_soc_dapm_new_controls(dapm, aic3x_dapm_mclk_widgets, 1);
++ } else {
++ dev_warn(component->dev, "DAPM MCLK widgets not set\n");
++ }
++
++
+ switch (aic3x->model) {
+ case AIC3X_MODEL_3X:
+ case AIC3X_MODEL_33:
+@@ -1061,6 +1075,7 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
+ data |= (0x03 << 4);
+ break;
+ }
++
+ snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, data);
+
+ /* Fsref can be 44100 or 48000 */
+@@ -1237,6 +1252,7 @@ static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+ clk_id << CLKDIV_IN_SHIFT);
+
+ aic3x->sysclk = freq;
++
+ return 0;
+ }
+
+@@ -1688,6 +1704,13 @@ static void aic3x_remove(struct snd_soc_component *component)
+ &aic3x->disable_nb[i].nb);
+ }
+
++static int aic3x_of_xlate_dai_id(struct snd_soc_component *component,
++ struct device_node *endpoint)
++{
++ /* return dai id 0, whatever the endpoint index */
++ return 0;
++}
++
+ static const struct snd_soc_component_driver soc_component_dev_aic3x = {
+ .set_bias_level = aic3x_set_bias_level,
+ .probe = aic3x_probe,
+@@ -1698,6 +1721,7 @@ static const struct snd_soc_component_driver soc_component_dev_aic3x = {
+ .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets),
+ .dapm_routes = intercon,
+ .num_dapm_routes = ARRAY_SIZE(intercon),
++ .of_xlate_dai_id = aic3x_of_xlate_dai_id,
+ .use_pmdown_time = 1,
+ .endianness = 1,
+ .non_legacy_dai_naming = 1,
+@@ -1846,6 +1870,14 @@ static int aic3x_i2c_probe(struct i2c_client *i2c,
+
+ aic3x->model = id->driver_data;
+
++ aic3x->mclk_handle = devm_clk_get(&i2c->dev, "MCLK");
++ if (IS_ERR(aic3x->mclk_handle)) {
++ dev_err(&i2c->dev, "Failed to request MCLK\n");
++ if (PTR_ERR(aic3x->mclk_handle) != -ENOENT)
++ return PTR_ERR(aic3x->mclk_handle);
++ aic3x->mclk_handle = NULL;
++ }
++
+ if (gpio_is_valid(aic3x->gpio_reset) &&
+ !aic3x_is_shared_reset(aic3x)) {
+ ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-06-rtc.config b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-06-rtc.config
new file mode 100644
index 0000000..0e12776
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-06-rtc.config
@@ -0,0 +1 @@
+CONFIG_RTC_DRV_RV3028=y
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-07-eeprom.config b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-07-eeprom.config
new file mode 100644
index 0000000..f9caea5
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-07-eeprom.config
@@ -0,0 +1 @@
+CONFIG_EEPROM_AT24=y
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-08-spi-nor.config b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-08-spi-nor.config
new file mode 100644
index 0000000..ed69248
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-08-spi-nor.config
@@ -0,0 +1,2 @@
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_SPI_NOR=y
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-09-audio.config b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-09-audio.config
new file mode 100644
index 0000000..45ea20f
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-09-audio.config
@@ -0,0 +1,3 @@
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_SOC_TLV320AIC3X=m
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-10-peb-hdmi.config b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-10-peb-hdmi.config
new file mode 100644
index 0000000..9cbb7b3
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-10-peb-hdmi.config
@@ -0,0 +1 @@
+CONFIG_DRM_I2C_NXP_TDA998X=y
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-11-wifi-r8712u-support.config b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-11-wifi-r8712u-support.config
new file mode 100644
index 0000000..f1ab9d4
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-11-wifi-r8712u-support.config
@@ -0,0 +1,95 @@
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+CONFIG_STAGING=y
+# CONFIG_PRISM2_USB is not set
+# CONFIG_COMEDI is not set
+# CONFIG_RTLLIB is not set
+# CONFIG_RTL8723BS is not set
+CONFIG_R8712U=m
+# CONFIG_R8188EU is not set
+# CONFIG_VT6656 is not set
+
+#
+# IIO staging drivers
+#
+
+#
+# Accelerometers
+#
+# CONFIG_ADIS16203 is not set
+# CONFIG_ADIS16240 is not set
+
+#
+# Analog to digital converters
+#
+# CONFIG_AD7606 is not set
+# CONFIG_AD7780 is not set
+# CONFIG_AD7816 is not set
+# CONFIG_AD7192 is not set
+# CONFIG_AD7280 is not set
+
+#
+# Analog digital bi-direction converters
+#
+# CONFIG_ADT7316 is not set
+
+#
+# Capacitance to digital converters
+#
+# CONFIG_AD7150 is not set
+# CONFIG_AD7152 is not set
+# CONFIG_AD7746 is not set
+
+#
+# Direct Digital Synthesis
+#
+# CONFIG_AD9832 is not set
+# CONFIG_AD9834 is not set
+
+#
+# Network Analyzer, Impedance Converters
+#
+# CONFIG_AD5933 is not set
+
+#
+# Active energy metering IC
+#
+# CONFIG_ADE7854 is not set
+
+#
+# Resolver to digital converters
+#
+# CONFIG_AD2S90 is not set
+# CONFIG_AD2S1210 is not set
+
+#
+# Speakup console speech
+#
+# CONFIG_SPEAKUP is not set
+# CONFIG_STAGING_MEDIA is not set
+
+#
+# Android
+#
+# CONFIG_STAGING_BOARD is not set
+# CONFIG_LTE_GDM724X is not set
+# CONFIG_MTD_SPINAND_MT29F is not set
+# CONFIG_GS_FPGABOOT is not set
+# CONFIG_UNISYSSPAR is not set
+# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
+# CONFIG_FB_TFT is not set
+# CONFIG_WILC1000_SDIO is not set
+# CONFIG_WILC1000_SPI is not set
+# CONFIG_MOST is not set
+# CONFIG_KS7010 is not set
+# CONFIG_GREYBUS is not set
+# CONFIG_PI433 is not set
+# CONFIG_MTK_MMC is not set
+
+#
+# Gasket devices
+#
+# CONFIG_XIL_AXIS_FIFO is not set
+# CONFIG_EROFS_FS is not set
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-12-add-dp83867-phy-support.config b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-12-add-dp83867-phy-support.config
new file mode 100644
index 0000000..d6fc0ca
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-12-add-dp83867-phy-support.config
@@ -0,0 +1 @@
+CONFIG_DP83867_PHY=y
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-13-add-pca953x-led-support.config b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-13-add-pca953x-led-support.config
new file mode 100644
index 0000000..ccaf379
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp/4.19/fragment-13-add-pca953x-led-support.config
@@ -0,0 +1,4 @@
+# CONFIG_GPIO_PCA953X is not set
+CONFIG_LEDS_PCA9532=y
+CONFIG_LEDS_PCA9532_GPIO=y
+CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp_4.19.bbappend b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp_4.19.bbappend
new file mode 100644
index 0000000..751b52c
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-kernel/linux/linux-stm32mp_4.19.bbappend
@@ -0,0 +1,25 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+
+SRC_URI += " \
+ file://${LINUX_VERSION}/4.19.9/0065-ARM-stm32mp1-r0-rc1-add-phycore-stm32mp1xx-alpha1-machine.patch \
+"
+
+KERNEL_CONFIG_FRAGMENTS += "${WORKDIR}/fragments/4.19/fragment-06-rtc.config"
+KERNEL_CONFIG_FRAGMENTS += "${WORKDIR}/fragments/4.19/fragment-07-eeprom.config"
+KERNEL_CONFIG_FRAGMENTS += "${WORKDIR}/fragments/4.19/fragment-08-spi-nor.config"
+KERNEL_CONFIG_FRAGMENTS += "${WORKDIR}/fragments/4.19/fragment-09-audio.config"
+KERNEL_CONFIG_FRAGMENTS += "${WORKDIR}/fragments/4.19/fragment-10-peb-hdmi.config"
+KERNEL_CONFIG_FRAGMENTS += "${WORKDIR}/fragments/4.19/fragment-11-wifi-r8712u-support.config"
+KERNEL_CONFIG_FRAGMENTS += "${WORKDIR}/fragments/4.19/fragment-12-add-dp83867-phy-support.config"
+KERNEL_CONFIG_FRAGMENTS += "${WORKDIR}/fragments/4.19/fragment-13-add-pca953x-led-support.config"
+
+SRC_URI += "file://4.19/fragment-06-rtc.config;subdir=fragments"
+SRC_URI += "file://4.19/fragment-07-eeprom.config;subdir=fragments"
+SRC_URI += "file://4.19/fragment-08-spi-nor.config;subdir=fragments"
+SRC_URI += "file://4.19/fragment-09-audio.config;subdir=fragments"
+SRC_URI += "file://4.19/fragment-10-peb-hdmi.config;subdir=fragments"
+SRC_URI += "file://4.19/fragment-11-wifi-r8712u-support.config;subdir=fragments"
+SRC_URI += "file://4.19/fragment-12-add-dp83867-phy-support.config;subdir=fragments"
+SRC_URI += "file://4.19/fragment-13-add-pca953x-led-support.config;subdir=fragments"
+
+
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-st/images/phytec-common-tools.inc b/dynamic-layers/stm-st-stm32mp/recipes-st/images/phytec-common-tools.inc
new file mode 100644
index 0000000..85e667d
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-st/images/phytec-common-tools.inc
@@ -0,0 +1,8 @@
+CORE_IMAGE_EXTRA_INSTALL_append = " \
+ net-tools \
+ tcpdump \
+ iperf3 \
+ rs485test \
+ serial-test \
+ spidev-test \
+"
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-st/images/st-image-core.bbappend b/dynamic-layers/stm-st-stm32mp/recipes-st/images/st-image-core.bbappend
new file mode 100644
index 0000000..430651d
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-st/images/st-image-core.bbappend
@@ -0,0 +1 @@
+require phytec-common-tools.inc
diff --git a/dynamic-layers/stm-st-stm32mp/recipes-st/images/st-image-weston.bbappend b/dynamic-layers/stm-st-stm32mp/recipes-st/images/st-image-weston.bbappend
new file mode 100644
index 0000000..430651d
--- /dev/null
+++ b/dynamic-layers/stm-st-stm32mp/recipes-st/images/st-image-weston.bbappend
@@ -0,0 +1 @@
+require phytec-common-tools.inc
diff --git a/recipes-devtools/spitest/spidev-test_git.bb b/recipes-devtools/spitest/spidev-test_git.bb
new file mode 100644
index 0000000..9927aa7
--- /dev/null
+++ b/recipes-devtools/spitest/spidev-test_git.bb
@@ -0,0 +1,21 @@
+DESCRIPTION = "Spidev test application"
+HOMEPAGE = "https://github.com/rm-hull/spidev-test"
+SECTION = "utils"
+LICENSE = "GPLv2"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=a23a74b3f4caf9616230789d94217acb"
+SRCREV = "0b7ecd60c56de6eb36ed553cfa9ebecf34aea8c1"
+
+SRC_URI = "git://github.com/rm-hull/spidev-test.git;branch=master;protocol=git"
+
+S = "${WORKDIR}/git/"
+
+
+do_compile() {
+ ${CC} ${CFLAGS} spidev_test.c -o spidev_test ${LDFLAGS}
+}
+
+do_install() {
+ install -d ${D}${bindir}
+ install -m 0755 spidev_test ${D}${bindir}
+}
+
diff --git a/scripts/envsetup.sh b/scripts/envsetup.sh
new file mode 100644
index 0000000..8551492
--- /dev/null
+++ b/scripts/envsetup.sh
@@ -0,0 +1,1438 @@
+#!/bin/bash -
+
+_FORMAT_PATTERN='£-£'
+_SITECONFSAMPLE_PATH=$(dirname $(realpath ${BASH_SOURCE}))
+
+#----------------------------------------------
+# Set supported Linux Distrib Release
+#
+_SUPPORTED_LINUX_DISTRIB="Ubuntu"
+_SUPPORTED_UBUNTU_RELEASE="16.04 18.04"
+
+#----------------------------------------------
+# Set default layer root
+#
+if [ -z $META_LAYER_ROOT ]; then
+ _META_LAYER_ROOT=layers/meta-st
+else
+ _META_LAYER_ROOT=$META_LAYER_ROOT
+fi
+
+if [ -z $META_LAYER_BSP ]; then
+ _META_LAYER_BSP=layers/meta-phytec
+else
+ _META_LAYER_BSP=$META_LAYER_BSP
+fi
+
+
+#----------------------------------------------
+# Set ROOTOE for oe sdk baseline
+#
+ROOTOE=$PWD
+while test ! -d "${ROOTOE}/${_META_LAYER_ROOT}" && test "${ROOTOE}" != "/"
+do
+ ROOTOE=$(dirname ${ROOTOE})
+done
+if test "${ROOTOE}" == "/"
+then
+ echo "[ERROR] you're trying to launch the script outside oe sdk tree"
+ return 1
+fi
+
+######################################################
+# FUNCTION / ALIAS
+# --
+#
+
+######################################################
+# Envsetup help
+#
+stoe_help() {
+ echo ""
+ echo "==========================================================================="
+ _stoe_help_usage
+ echo ""
+ echo "==========================================================================="
+ _stoe_help_option
+ echo ""
+ echo "==========================================================================="
+ _stoe_help_extra
+ echo ""
+ echo "==========================================================================="
+ echo ""
+}
+
+_stoe_help_usage() {
+ echo "Usage:"
+ echo " source ${BASH_SOURCE#$PWD/} [OPTION]"
+ echo ""
+ echo "Description:"
+ echo " This script allows to enable OpenEmbedded build environment."
+ echo " It will generate if needed the bblayers.conf and local.conf files according"
+ echo " to the DISTRO and MACHINE you want to use and configure by default build"
+ echo " folder as: 'build-<DISTRO>-<MACHINE>'."
+ echo " Note that it has to be sourced from baseline root."
+}
+_stoe_help_option() {
+ echo "Options:"
+ echo " --help"
+ echo " Print this message"
+ echo " --reset"
+ echo " Remove existing configuration files and restore original ones"
+ echo " --no-ui"
+ echo " Disable UI for DISTRO and MACHINE selection"
+ echo " <BUILD_DIR>"
+ echo " Provide specific build folder (should start with 'build' prefix)"
+}
+_stoe_help_extra() {
+ echo "Extra configuration:"
+ echo " Avoid selection by user:"
+ echo " Before sourcing the script, user can define any of:"
+ echo " BUILD_DIR=<BUILD_DIR> : set specific build folder"
+ echo " DISTRO=<DISTRO> : set specific DISTRO config"
+ echo " MACHINE=<MACHINE> : set specific MACHINE config"
+ echo " Example:"
+ echo " $> DISTRO=nodistro MACHINE=stm32mp1 source ${BASH_SOURCE#$PWD/}"
+ echo ""
+ echo " Override default script settings:"
+ echo " DL_DIR:"
+ echo " Override with FORCE_DL_CACHEPREFIX var:"
+ echo " $> FORCE_DL_CACHEPREFIX=<DOWNLOAD_CACHE_PATH> source ${BASH_SOURCE#$PWD/}"
+ echo " This configures '<FORCE_DL_CACHEPREFIX>/oe-downloads' as download"
+ echo " cache folder in site.conf file."
+ echo " SSTATE_DIR:"
+ echo " Override with FORCE_SSTATE_CACHEPREFIX var:"
+ echo " $> FORCE_SSTATE_CACHEPREFIX=<SSTATE_CACHE_PATH> source ${BASH_SOURCE#$PWD/}"
+ echo " This configures '<FORCE_SSTATE_CACHEPREFIX>/oe-sstate-cache' as"
+ echo " sstate cache folder in site.conf file."
+ echo " SOURCE_MIRROR_URL:"
+ echo " Override with FORCE_SOURCE_MIRROR_URL var:"
+ echo " $> FORCE_SOURCE_MIRROR_URL=<SOURCE_MIRROR_URL_PATH> source ${BASH_SOURCE#$PWD/}"
+ echo " This configures 'SOURCE_MIRROR_URL = <FORCE_SOURCE_MIRROR_URL>' as"
+ echo " PREMIRRORS when fetching source in site.conf file."
+ echo " SSTATE_MIRROR_URL:"
+ echo " Override with FORCE_SSTATE_MIRROR_URL var:"
+ echo " $> FORCE_SSTATE_MIRROR_URL=<SSTATE_MIRROR_URL_PATH> source ${BASH_SOURCE#$PWD/}"
+ echo " This configures 'file://.* <FORCE_SSTATE_MIRROR_URL>/PATH;downloadfilename=PATH'"
+ echo " as sstate mirror in site.conf file."
+ echo ""
+ echo " Configure SDKMACHINE:"
+ echo " By default SDKMACHINE is same as current HOST, but this can be override"
+ echo " if user defines SDKMACHINE=<SDKMACHINE> before sourcing the script."
+ echo " Example: on 64 bits HOST, set 32 bits SDK build"
+ echo " $> SDKMACHINE=i586 source ${BASH_SOURCE#$PWD/}"
+ echo ""
+ echo " Define BSP_DEPENDENCY:"
+ echo " For specific machine, outside of meta-st layers, we may need to append"
+ echo " specific layers to bblayers.conf file when sourcing environement setup file"
+ echo " A specific var is available to provide the list of layer path (starting from"
+ echo " baseline root): BSP_DEPENDENCY"
+ echo " Example:"
+ echo " $> BSP_DEPENDENCY='<layer_path1> <layer_path2>' source ${BASH_SOURCE#$PWD/}"
+ echo ""
+ echo " Configure META_LAYER_ROOT:"
+ echo " By default the script run using meta-st as default layer root, but this can"
+ echo " be changed if you set META_LAYER_ROOT (starting from baseline root)"
+ echo " Example:"
+ echo " $> META_LAYER_ROOT=openembedded-core source ${BASH_SOURCE#$PWD/}"
+}
+
+######################################################
+# provide full list of STOE utilities available
+_stoe_utilities() {
+ echo "==========================================================================="
+ echo "STOE Utilities:"
+ echo " stoe_list_env : list all ST environement variables"
+ echo " stoe_list_images [LAYER_PATH] : list all images available in LAYER_PATH"
+ echo " stoe_config_summary [BUILD_DIR] : list config summary for BUILD_DIR"
+ echo " stoe_source_premirror_disable : disable SOURCE_MIRROR_URL in conf file"
+ echo " stoe_source_premirror_enable : enable SOURCE_MIRROR_URL in conf file"
+ echo " stoe_sstate_mirror_disable : disable sstate-mirror usage"
+ echo " stoe_sstate_mirror_enable : enable sstate-mirror usage"
+ echo "==========================================================================="
+}
+
+######################################################
+# alias function: list all ST environment variables
+#
+stoe_list_env() {
+ echo "==========================================================================="
+ echo "List of environment variables available:"
+ echo " BUILDDIR = $BUILDDIR"
+ echo " ST_OE_DISTRO_CODENAME = $ST_OE_DISTRO_CODENAME"
+ echo "==========================================================================="
+}
+
+######################################################
+# init UI_CMD if needed
+_stoe_set_env_init() {
+ if [[ $_ENABLE_UI -eq 1 ]] && [[ -z "${UI_CMD}" ]]; then
+ # Init dialog box command if dialog or whiptail is available
+ command -v dialog > /dev/null 2>&1 && UI_CMD='dialog'
+ command -v whiptail > /dev/null 2>&1 && UI_CMD='whiptail'
+ fi
+}
+
+######################################################
+# alias function: set all ST environment variables
+#
+stoe_set_env() {
+ export ST_OE_DISTRO_CODENAME=$_DISTRO_CODENAME
+}
+
+######################################################
+# extract requested VAR from conf files for BUILD_DIR provided
+_stoe_config_read() {
+ local builddir=$(realpath $1)
+ local stoe_var=$2
+ local findconfig=""
+ if ! [[ -z $(grep -Rs "^[ \t]*$stoe_var[ \t]*=" $builddir/conf/*.conf) ]]; then
+ # Config defined as "=" in conf file
+ findconfig=$(grep -Rs "^[ \t]*$stoe_var[ \t]*=" $builddir/conf/*.conf)
+ elif ! [[ -z $(grep -Rs "^[ \t]*$stoe_var[ \t]*?*=" $builddir/conf/*.conf) ]]; then
+ # Config defined as "?=" in conf file
+ findconfig=$(grep -Rs "^[ \t]*$stoe_var[ \t]*?*=" $builddir/conf/*.conf)
+ elif ! [[ -z $(grep -Rs "^[#]*$stoe_var[ \t]*=" $builddir/conf/*.conf) ]]; then
+ findconfig="\<disable\>"
+ else
+ # Config not found
+ findconfig="\<no-custom-config-set\>"
+ fi
+ # Format config
+ local formatedconfig=$(echo $findconfig | sed -e 's|^.*"\(.*\)".*$|\1|g;s|\${TOPDIR}|\${builddir}|')
+ # Expand and export config
+ eval echo "$formatedconfig"
+}
+
+######################################################
+# alias function: display current configuration
+#
+stoe_config_summary() {
+ local builddir=""
+ if [[ $# == 0 ]]; then
+ # Override builddir in case of none argument provided
+ builddir=$BUILDDIR
+ elif [ $(realpath $1) ]; then
+ # Use provided dir as builddir
+ builddir=$(realpath $1)
+ else
+ echo "[ERROR] '$1' is not an existing BUILD_DIR."
+ echo ""
+ return 1
+ fi
+ echo ""
+ echo "==========================================================================="
+ echo "Configuration files have been created for the following configuration:"
+ echo ""
+ echo " DISTRO : " $(_stoe_config_read $builddir DISTRO)
+ echo " DISTRO_CODENAME : " $ST_OE_DISTRO_CODENAME
+ echo " MACHINE : " $(_stoe_config_read $builddir MACHINE)
+ echo " BB_NUMBER_THREADS : " $(_stoe_config_read $builddir BB_NUMBER_THREADS)
+ echo " PARALLEL_MAKE : " $(_stoe_config_read $builddir PARALLEL_MAKE)
+ echo ""
+ echo " BUILD_DIR : " $(basename $builddir)
+ echo " DOWNLOAD_DIR : " $(_stoe_config_read $builddir DL_DIR)
+ echo " SSTATE_DIR : " $(_stoe_config_read $builddir SSTATE_DIR)
+ echo ""
+ echo " SOURCE_MIRROR_URL : " $(_stoe_config_read $builddir SOURCE_MIRROR_URL)
+ echo " SSTATE_MIRRORS : " $(_stoe_config_read $builddir SSTATE_MIRRORS | sed 's|^.*\(http:.*\)/PATH.*$|\1|')
+ echo ""
+ echo " WITH_EULA_ACCEPTED: " $(_stoe_config_read $builddir ACCEPT_EULA_$(_stoe_config_read $builddir MACHINE) | sed 's|0|NO|;s|1|YES|')
+ echo ""
+ echo "==========================================================================="
+ echo ""
+}
+
+######################################################
+# extract description for images provided
+_stoe_list_images_descr() {
+ for l in $1;
+ do
+ local image=$(echo $l | sed -e 's#^.*/\([^/]*\).bb$#\1#')
+ if [ ! -z "$(grep "^SUMMARY[ \t]*=" $l)" ]; then
+ local descr=$(grep "^SUMMARY[ \t]*=" $l | sed -e 's/^.*"\(.*\)["\]$/\1/')
+ else
+ local descr=$(grep "^DESCRIPTION[ \t]*=" $l | sed -e 's/^.*"\(.*\)["\]$/\1/')
+ fi
+ if [ -z "$descr" ] && [ "$2" == "ERR" ]; then
+ descr="[ERROR] No description available"
+ fi
+ printf " %-33s - $descr\n" $image
+ done
+}
+
+######################################################
+# alias function: list all images available
+#
+stoe_list_images() {
+ local metalayer=""
+ if [ "$#" = "0" ]; then
+ echo "[ERROR] missing layer path."
+ return 1
+ elif [ -e $(realpath $1)/conf/layer.conf ] || [ "$(realpath $1)" = "$(realpath ${ROOTOE}/${_META_LAYER_ROOT})" ]; then
+ # Use provided dir as metalayer
+ metalayer=$(realpath $1)
+ else
+ echo "[ERROR] '$1' is not an existing layer."
+ echo ""
+ return 1
+ fi
+ local err=$2
+ local filter=$3
+
+ local LIST=$(find $metalayer/ -type d \( -name '.git' -o -name 'source*' -o -name 'script*' \) -prune -o -type f -wholename '*/images/*.bb' -not -wholename '*/meta-skeleton/*' | grep '.*/images/.*\.bb' | sort)
+
+ if [ "$filter" = "FILTER" ]; then
+ local LAYERS_LIST=$(find $metalayer/ -type d \( -name '.git' -o -name 'source*' -o -name 'script*' \) -prune -o -type f -wholename '*/conf/layer.conf' -not -wholename '*/meta-skeleton/*' | grep '.*/conf/layer\.conf' | sed 's#/conf/layer.conf##' | sort)
+ # Filter for layer available in current bblayers.conf file
+ unset LAYERS_SET
+ for l in ${LAYERS_LIST}; do
+ if ! [[ -z $(grep "${l#$(dirname $BUILDDIR)/}[ '\"]" $BUILDDIR/conf/bblayers.conf) ]]; then
+ LAYERS_SET+=(${l})
+ fi
+ done
+ if [ -z "${#LAYERS_SET[@]}" ]; then
+ echo "[WARNING] None of the layers from $metalayer are defined in current $(basename $BUILDDIR)/conf/bblayers.conf file."
+ echo
+ return
+ fi
+ # Filter images from enabled layers
+ unset IMAGE_SET
+ for ITEM in ${LAYERS_SET[@]}; do
+ for i in ${LIST}; do
+ if [ "${i#$ITEM/}" != "$i" ]; then
+ IMAGE_SET+=(${i})
+ fi
+ done
+ done
+ if [ -z "${#IMAGE_SET[@]}" ]; then
+ echo "[WARNING] From the layers of $metalayer enable in your $(basename $BUILDDIR)/conf/bblayers.conf file, there is no image available for build."
+ echo
+ return
+ fi
+ LIST="${IMAGE_SET[@]}"
+ fi
+
+ echo ""
+ echo "==========================================================================="
+ echo "Available images for '$metalayer' layer are:"
+ echo ""
+ _stoe_list_images_descr "$LIST" "$err"
+ echo ""
+}
+
+######################################################
+# alias function: disable ST premirror
+#
+stoe_source_premirror_disable() {
+ if [ -e $BUILDDIR/conf/site.conf ]; then
+ if [ -z "$(grep SOURCE_MIRROR_URL $BUILDDIR/conf/site.conf)" ]; then
+ echo "[WARNING] no SOURCE_MIRROR_URL entry in site.conf from $BUILDDIR/conf/"
+ echo "Nothing to do..."
+ else
+ echo ">>> DISABLE SOURCE_MIRROR_URL in $BUILDDIR/conf/site.conf"
+ echo ">>> Default to default one from DISTRO or MACHINE settings (if any)"
+ sed -e 's|^[ /t]*\(SOURCE_MIRROR_URL.*\)$|#\1|g' -i $BUILDDIR/conf/site.conf
+ fi
+ else
+ echo "[WARNING] site.conf not found in $BUILDDIR/conf"
+ echo "Nothing to do..."
+ fi
+}
+
+######################################################
+# alias function: enable ST premirror
+#
+stoe_source_premirror_enable() {
+ if [ -e $BUILDDIR/conf/site.conf ]; then
+ if [ -z "$(grep SOURCE_MIRROR_URL $BUILDDIR/conf/site.conf)" ]; then
+ echo "[ERROR] missing SOURCE_MIRROR_URL definition in $BUILDDIR/conf/site.conf..."
+ echo "Nothing done!"
+ else
+ echo ">>> ENABLE SOURCE_MIRROR_URL in $BUILDDIR/conf/site.conf"
+ sed -e 's|^.*\(SOURCE_MIRROR_URL.*\)$|\1|g' -i $BUILDDIR/conf/site.conf
+ fi
+ else
+ echo "[ERROR] missing site.conf in $BUILDDIR/conf/..."
+ echo "Nothing done!"
+ fi
+}
+
+######################################################
+# alias function: disable sstate-cache mirror
+#
+stoe_sstate_mirror_disable() {
+ if [ -e $BUILDDIR/conf/site.conf ]; then
+ if [ -z "$(grep SSTATE_MIRRORS $BUILDDIR/conf/site.conf)" ]; then
+ echo "[WARNING] no SSTATE_MIRRORS entry in site.conf from $BUILDDIR/conf/"
+ echo "Nothing to do..."
+ else
+ echo ">>> DISABLE SSTATE_MIRRORS in $BUILDDIR/conf/site.conf"
+ sed -e 's|^[ /t]*\(SSTATE_MIRRORS.*\)$|#\1|g' -i $BUILDDIR/conf/site.conf
+ fi
+ else
+ echo "[WARNING] site.conf not found in $BUILDDIR/conf"
+ echo "Nothing to do..."
+ fi
+}
+
+######################################################
+# alias function: enable sstate-cache mirror
+#
+stoe_sstate_mirror_enable() {
+ if [ -e $BUILDDIR/conf/site.conf ]; then
+ if [ -z "$(grep SSTATE_MIRRORS $BUILDDIR/conf/site.conf)" ]; then
+ echo "[ERROR] missing SSTATE_MIRRORS definition in $BUILDDIR/conf/site.conf..."
+ echo "Nothing done!"
+ else
+ echo ">>> ENABLE SSTATE_MIRRORS in $BUILDDIR/conf/site.conf"
+ sed -e 's|^.*\(SSTATE_MIRRORS.*\)$|\1|g' -i $BUILDDIR/conf/site.conf
+ fi
+ else
+ echo "[ERROR] missing site.conf in $BUILDDIR/conf/..."
+ echo "Nothing done!"
+ fi
+}
+
+######################################################
+# Get ST distro code name to udpate DL and SSTATE path in site.conf
+#
+get_distrocodename()
+{
+ #get distro related folder from layer root
+ local distro_dir=$(find ${ROOTOE}/$_META_LAYER_ROOT/ -type d \( -name '.git' -o -name '.repo' -o -name 'build*' -o -name 'source*' -o -name 'script*' \) -prune -o -type d -wholename '*/conf/distro' | grep '.*/conf/distro')
+ if [ -z "$distro_dir" ]; then
+ echo ""
+ echo "[WARNING] No */conf/distro folder available in $_META_LAYER_ROOT layer"
+ echo "[WARNING] Init ST_OE_DISTRO_CODENAME to NONE"
+ echo ""
+ _DISTRO_CODENAME="NONE"
+ return
+ fi
+
+ #gather DISTRO_CODENAME values
+ _DISTRO_CODENAME=$(grep -Rs '^DISTRO_CODENAME' $distro_dir | sed 's|.*DISTRO_CODENAME[ \t]*=[ \t]*"\(.*\)"[ \t]*$|\1|g'| sort -u)
+
+ #make sure that DISTRO_CODENAME is defined and has only one value
+ if [ -z "$_DISTRO_CODENAME" ] ; then
+ echo ""
+ echo "[ERROR] No DISTRO_CODENAME definition found in folder:"
+ echo "$distro_dir"
+ echo ""
+ return 1
+ elif [ "$(echo $_DISTRO_CODENAME | wc -w)" -gt 1 ]; then
+ echo ""
+ echo "[ERROR] Found different DISTRO_CODENAME definition in $_META_LAYER_ROOT layer. Please cleanup/clarify:"
+ echo "$_DISTRO_CODENAME"
+ echo ""
+ return 1
+ fi
+}
+
+######################################################
+# ST EULA acceptance management based on 96boards implementation scheme:
+#
+# Handle EULA , if needed. This is a generic method to handle BSPs
+# that might (or not) come with a EULA. If a machine has a EULA, we
+# assume that its corresponding layers has conf/EULA/$MACHINE file
+# with the EULA text, which we will display to the user and request
+# for acceptance. If accepted, the variable ACCEPT_EULA_$MACHINE is
+# set to 1 in auto.conf, which can later be used by the BSP.
+# If the env variable EULA_$MACHINE is set it is used by default,
+# without prompting the user.
+#
+# Update the _EULA_ACCEPT with proper value for update in site.conf
+#
+eula_check() {
+ # Reset by default ACCEPT_EULA_$MACHINE to false
+ _EULA_ACCEPT=0
+
+ # Init environment bypath variable name
+ # Remove any '-' and '.' from bash variable name
+ local eula_machine="EULA_$(echo "$MACHINE" | sed 's/-//g;s/\.//g')"
+
+ # Get machine path folder to check if there is an associated EULA
+ local machine_file=$(find ${ROOTOE}/$_META_LAYER_BSP/ -type d \( -name '.git' -o -name '.repo' -o -name 'build*' -o -name 'source*' -o -name 'script*' \) -prune -o -type f -name "$MACHINE.conf" | grep "/machine/$MACHINE.conf")
+
+ # Make sure machine name is uniq in _META_LAYER_ROOT to avoid detecting wrong EULA file
+ if [ "$(echo $machine_file | wc -w)" -gt 1 ]; then
+ echo "[ERROR] More than one $MACHINE found in ${_META_LAYER_BSP}. Please cleanup/clarify:"
+ echo "${machine_file#*${ROOTOE}/}"
+ echo
+ return 1
+ else
+ # Init EULA licence file path
+ local eula_file=$(echo ${machine_file} | sed 's|/machine/\(.*\)\.conf$|/eula/\1|')
+ fi
+
+ if [ -f "${eula_file}" ]; then
+ # Init EULA_ENABLE for local.conf update
+ _EULA_ENABLE="YES"
+ # NOTE: indirect reference / dynamic variable
+ if [ -n "${!eula_machine}" ]; then
+ # The EULA_$MACHINE variable is set in the environment, so we just use it to bypath EULA acceptance check
+ _EULA_ACCEPT=${!eula_machine}
+ else
+ # Ask user for EULA acceptance
+ eula_askuser "${eula_file}"
+ fi
+ else
+ echo "[WARNING] No eula file found : not able to configure EULA agreement or not."
+ fi
+}
+
+######################################################
+# Ask user for EULA acceptance for licence file provided
+#
+eula_askuser() {
+ # License file provided
+ local EulaFile=$1
+
+ # Init EULA introduction text
+ EulaIntroFile=$(mktemp)
+ echo "\
+The BSP for $MACHINE depends on packages and firmware which are covered by an \
+End User License Agreement (EULA). To have the right to use these binaries \
+in your images, you need to read and accept the following...\
+" > $EulaIntroFile
+
+ # Select mode to dialogue with user
+ if ! [[ -z "$DISPLAY" ]] && ! [[ -z "${UI_CMD}" ]]; then
+ # UI mode (through dialogue boxes)
+ if (${UI_CMD} --title "EULA management" --yesno "$(cat $EulaIntroFile)" 0 0 --yes-button "Read the EULA" --no-button "EXIT"); then
+ if (${UI_CMD} --title "EULA acceptance" --yesno "$(cat $EulaFile)" 0 0 --yes-button "Accept EULA" --no-button "EXIT"); then
+ _EULA_ACCEPT=1
+ fi
+ fi
+ else
+ # Default console mode
+ local answer=
+ local wrong_answer=0
+ cat $EulaIntroFile
+ while [ -z "$answer" ] && [ "$wrong_answer" -lt "$TRIALMAX" ]; do
+ echo -n "Would you like to read the EULA ? (y/n) "
+ read -r -t $READTIMEOUT answer
+ if [ "$?" -gt "128" ]; then
+ echo
+ echo "[WARNING] Timeout reached"
+ echo "[WARNING] Default answer to 'no'."
+ echo
+ answer="no"
+ elif (echo -n $answer | grep -q -e "^[yY][a-zA-Z]*$"); then
+ answer="yes"
+ elif (echo -n $answer | grep -q -e "^[nN][a-zA-Z]*$"); then
+ answer="no"
+ else
+ answer=
+ wrong_answer=$((wrong_answer+1))
+ if [ "$wrong_answer" -eq "$TRIALMAX" ]; then
+ echo
+ echo "[WARNING] Maximum trials reached"
+ echo "[WARNING] Default answer to 'no'."
+ echo
+ answer="no"
+ fi
+ fi
+ done
+ if [ "$answer" == "yes" ]; then
+ # Display EULA to user
+ echo
+ more -d "$EulaFile"
+ echo
+ answer=
+ wrong_answer=0
+ while [ -z "$answer" ] && [ "$wrong_answer" -lt "$TRIALMAX" ]; do
+ echo -n "Do you accept the EULA you just read? (y/n) "
+ read -r -t $READTIMEOUT answer
+ if [ "$?" -gt "128" ]; then
+ echo
+ echo "[WARNING] Timeout reached"
+ echo "[WARNING] Default answer to 'no'."
+ echo
+ answer="no"
+ elif (echo -n $answer | grep -q -e "^[yY][a-zA-Z]*$"); then
+ echo "EULA has been accepted."
+ _EULA_ACCEPT=1
+ elif (echo -n $answer | grep -q -e "^[nN][a-zA-Z]*$"); then
+ answer="no"
+ else
+ answer=
+ wrong_answer=$((wrong_answer+1))
+ if [ "$wrong_answer" -eq "$TRIALMAX" ]; then
+ echo
+ echo "[WARNING] Maximum trials reached"
+ echo "[WARNING] Default answer to 'no'."
+ echo
+ answer="no"
+ fi
+ fi
+ done
+ fi
+ if [ "$answer" == "no" ]; then
+ echo "[WARNING] Configure build without support of packages under EULA acceptance."
+ fi
+ fi
+ rm $EulaIntroFile
+}
+
+######################################################
+# Apply configuration to site.conf file
+#
+conf_siteconf()
+{
+ if [ -f conf/site.conf ]; then
+ echo "[WARNING] site.conf already exists. Nothing done..."
+ return
+ fi
+
+ _NCPU=$(grep '^processor' /proc/cpuinfo 2>/dev/null | wc -l)
+ # Sanity check that we have a valid number, if not then fallback to a safe default
+ [ "$_NCPU" -ge 1 ] 2>/dev/null || _NCPU=2
+
+ if [ -f ${_SITECONFSAMPLE_PATH}/site.conf.sample ]; then
+ # Copy default site.conf.sample to conf/site.conf
+ cp -f ${_SITECONFSAMPLE_PATH}/site.conf.sample conf/site.conf
+ # Update site.conf with expected settings
+ sed -e 's|##_DISTRO_CODENAME##|'"${_DISTRO_CODENAME}"'|g' -i conf/site.conf
+ sed -e 's|##_NCPU##|'"${_NCPU}"'|g' -i conf/site.conf
+ # Override default settings if requested
+ if ! [ -z "$FORCE_DL_CACHEPREFIX" ]; then
+ if ! [ -z "$(grep ^[#]*DL_DIR conf/site.conf)" ]; then
+ sed -e 's|^[#]*DL_DIR.*|DL_DIR = "'"${FORCE_DL_CACHEPREFIX}"'/oe-downloads"|g' -i conf/site.conf
+ else
+ echo "# Configure download cache folder" >> conf/site.conf
+ echo "DL_DIR = \"${FORCE_DL_CACHEPREFIX}/oe-downloads\"" >> conf/site.conf
+ fi
+ fi
+ if ! [ -z "$FORCE_SSTATE_CACHEPREFIX" ]; then
+ if ! [-z "$(grep ^[#]*SSTATE_DIR conf/site.conf)" ]; then
+ sed -e 's|^[#]*SSTATE_DIR.*|SSTATE_DIR = "'"${FORCE_SSTATE_CACHEPREFIX}"'/oe-sstate-cache"|g' -i conf/site.conf
+ else
+ echo "# Configure sstate cache folder" >> conf/site.conf
+ echo "SSTATE_DIR = \"${FORCE_SSTATE_CACHEPREFIX}/oe-sstate-cache\"" >> conf/site.conf
+ fi
+ else
+ # By default set sstate dir at root of baseline to share it among all build folders
+ sed -e 's|^[#]*SSTATE_DIR.*|SSTATE_DIR = "'"${ROOTOE}"'/sstate-cache"|g' -i conf/site.conf
+ fi
+ if ! [ -z "$FORCE_SOURCE_MIRROR_URL" ]; then
+ if ! [ -z "$(grep ^[#]*SOURCE_MIRROR_URL conf/site.conf)" ]; then
+ sed -e 's|^[#]*SOURCE_MIRROR_URL.*|SOURCE_MIRROR_URL = "'"${FORCE_SOURCE_MIRROR_URL}"'"|g' -i conf/site.conf
+ sed -e 's|^[#]*BB_GENERATE_MIRROR_TARBALLS = \"1\"|BB_GENERATE_MIRROR_TARBALLS = \"1\"|g' -i conf/site.conf
+ else
+ echo "# Configure sstate cache mirror URL" >> conf/site.conf
+ echo "SSTATE_MIRRORS = \"file://\.\* ${FORCE_SSTATE_MIRROR_URL}/PATH;downloadfilename=PATH\"" >> conf/site.conf
+ fi
+ fi
+ if ! [ -z "$FORCE_SSTATE_MIRROR_URL" ]; then
+ sed -e 's|^[#]*SSTATE_MIRRORS = ".*\(/PATH;.*\)"$|SSTATE_MIRRORS = "file://\.\* '"${FORCE_SSTATE_MIRROR_URL}"'\2"|g' -i conf/site.conf
+ fi
+ else
+ echo "[INFO] No 'site.conf.sample' file available at ${_SITECONFSAMPLE_PATH}. Create default one..."
+ cat >> conf/site.conf <<EOF
+#
+# local.conf covers user settings, site.conf covers site specific information
+# such as proxy server addresses and optionally any shared download location
+#
+
+# SITE_CONF_VERSION is increased each time build/conf/site.conf
+# changes incompatibly
+SCONF_VERSION = "1"
+
+EOF
+ # Configure default settings if requested
+ if ! [ -z "$FORCE_DL_CACHEPREFIX" ]; then
+ echo "# Configure download cache folder" >> conf/site.conf
+ echo "DL_DIR = \"${FORCE_DL_CACHEPREFIX}/oe-downloads\"" >> conf/site.conf
+ fi
+ if ! [ -z "$FORCE_SSTATE_CACHEPREFIX" ]; then
+ echo "# Configure sstate cache folder" >> conf/site.conf
+ echo "SSTATE_DIR = \"${FORCE_SSTATE_CACHEPREFIX}/oe-sstate-cache\"" >> conf/site.conf
+ fi
+ if ! [ -z "$FORCE_SOURCE_MIRROR_URL" ]; then
+ echo "# Configure download cache mirror URL" >> conf/site.conf
+ echo "SOURCE_MIRROR_URL = \"${FORCE_SOURCE_MIRROR_URL}\"" >> conf/site.conf
+ fi
+ if ! [ -z "$FORCE_SSTATE_MIRROR_URL" ]; then
+ echo "# Configure sstate cache mirror URL" >> conf/site.conf
+ echo "SSTATE_MIRRORS = \"file://\.\* ${FORCE_SSTATE_MIRROR_URL}/PATH;downloadfilename=PATH\"" >> conf/site.conf
+ fi
+ fi
+}
+
+######################################################
+# Apply configuration to local.conf file
+#
+conf_localconf()
+{
+ if [ -z "$(grep '^MACHINE =' conf/local.conf)" ]; then
+ # Apply selected MACHINE in local conf file
+ sed -e 's/^\(MACHINE.*\)$/#\1\nMACHINE = "'"$MACHINE"'"/' -i conf/local.conf
+ else
+ echo "[WARNING] MACHINE is already set in local.conf. Nothing done..."
+ fi
+ if [ -z "$(grep '^DISTRO =' conf/local.conf)" ]; then
+ # Apply selected DISTRO in local conf file
+ sed -e 's/^\(DISTRO.*\)$/#\1\nDISTRO = "'"$DISTRO"'"/' -i conf/local.conf
+ else
+ echo "[WARNING] DISTRO is already set in local.conf. Nothing done..."
+ fi
+
+ # Update local.conf with specific settings for EULA management
+ if [ "$_EULA_ENABLE" == "YES" ]; then
+ cat >> conf/local.conf <<EOF
+
+# =========================================================================
+# Set EULA acceptance
+# =========================================================================
+ACCEPT_EULA_$MACHINE = "${_EULA_ACCEPT}"
+EOF
+ fi
+
+ if ! [ -z "$SDKMACHINE" ]; then
+ # Apply specified SDKMACHINE in local conf file
+ if [ -z "$(grep '^SDKMACHINE =' conf/local.conf)" ]; then
+ sed -e 's/^[ #]\(SDKMACHINE .*\)$/#\1\nSDKMACHINE = "'"${SDKMACHINE}"'"/' -i conf/local.conf
+ else
+ echo "[WARNING] SDKMACHINE is already set in local.conf. Nothing done..."
+ fi
+ fi
+ if ! [ -z "$ST_ARCHIVER_ENABLE" ]; then
+ # Enable ST_ARCHIVER_ENABLE flag in local conf file
+ if [ -z "$(grep '^ST_ARCHIVER_ENABLE =' conf/local.conf)" ]; then
+ if [ -z "$(grep 'ST_ARCHIVER_ENABLE =' conf/local.conf)" ]; then
+ # Append ST_ARCHIVER_ENABLe flag to local.conf file
+ cat >> conf/local.conf <<EOF
+
+ST_ARCHIVER_ENABLE = "1"
+EOF
+ else
+ # Update local.conf file for ST_ARCHIVER_ENABLE flag
+ sed -e 's/^.*ST_ARCHIVER_ENABLE .*$/ST_ARCHIVER_ENABLE = \"1\"/g' -i conf/local.conf
+ fi
+ else
+ echo "[WARNING] ST_ARCHIVER_ENABLE is already set in local.conf. Nothing done..."
+ fi
+ fi
+
+ if ! [ -z "$OPENSTLINUX_RELEASE" ]; then
+ # Apply OPENSTLINUX_RELEASE flag: no '/' allowed, so truncate after last '/' if any
+ if [ -z "$(grep '^OPENSTLINUX_RELEASE =' conf/local.conf)" ]; then
+ cat >> conf/local.conf <<EOF
+
+# =========================================================================
+# Set OpenSTLinux release flag
+# =========================================================================
+OPENSTLINUX_RELEASE = "${OPENSTLINUX_RELEASE##*/}"
+EOF
+ else
+ echo "[WARNING] OPENSTLINUX_RELEASE is already set in local.conf. Nothing done..."
+ fi
+ fi
+}
+
+######################################################
+# Apply configuration to bblayer.conf file
+#
+conf_bblayerconf()
+{
+ local _MACH_CONF=$(find ${ROOTOE}/$_META_LAYER_BSP/ -type d \( -name '.git' -o -name '.repo' -o -name 'build*' -o -name 'source*' -o -name 'script*' \) -prune -o -type f -name "$MACHINE.conf" | grep "/machine/$MACHINE.conf")
+
+ if [ -n "${_MACH_CONF}" ]; then
+ # Get meta layer root for selected machine file
+ local _BSP_LAYER_REQUIRED=$(echo ${_MACH_CONF} | sed -n 's|.*'"$_META_LAYER_BSP"'\/\(.*\)\/conf\/machine\/.*|\1|p')
+ # Get any specific needed layer in machine file
+ local _LAYERS=$(grep '^#@NEEDED_BSPLAYERS:' $_MACH_CONF)
+ local _BSP=$(echo ${_LAYERS} |cut -f 2 -d ':')
+ # Append any required layer list to _BSP list
+ if [ -n "$BSP_DEPENDENCY" ]; then
+ _BSP="$BSP_DEPENDENCY $_BSP"
+ fi
+ if [ -n "${_BSP}" ]; then
+ cat >> conf/bblayers.conf <<EOF
+# BSP dependencies"
+EOF
+
+ for bsp in $_BSP; do
+ bsp_to_add=$(echo $bsp | tr -d ' ')
+ cat >> conf/bblayers.conf <<EOF
+BBLAYERS =+ "${ROOTOE}/$bsp_to_add"
+EOF
+ done
+ fi
+ if [ -n "$_BSP_LAYER_REQUIRED" -a \
+ "${_LAYERS#*${_BSP_LAYER_REQUIRED}}" = "${_LAYERS}" -a \
+ "$(grep "${_BSP_LAYER_REQUIRED}" conf/bblayers.conf)" == "" ]; then
+ cat >> conf/bblayers.conf <<EOF
+
+# specific bsp selected
+BBLAYERS =+ "${ROOTOE}/$_META_LAYER_BSP/$_BSP_LAYER_REQUIRED"
+EOF
+ fi
+ else
+ echo "[WARNING] Not able to find ${MACHINE}.conf file in ${_META_LAYER_BSP} : bblayer.conf not updated..."
+ fi
+}
+
+######################################################
+# Copy 'conf-notes.txt' from available template files to BUILDDIR
+#
+conf_notes()
+{
+ if [ -f ${_TEMPLATECONF}/conf-notes.txt ]; then
+ cp ${_TEMPLATECONF}/conf-notes.txt conf
+ elif [ -z "${_TEMPLATECONF}" ]; then
+ # '_TEMPLATECONF' is empty when dealing with 'nodistro' use case
+ # Copy then the default OE 'conf-notes.txt' file
+ if [ -f ${ROOTOE}/$_BUILDSYSTEM/meta/conf/conf-notes.txt ]; then
+ cp ${ROOTOE}/$_BUILDSYSTEM/meta/conf/conf-notes.txt conf
+ fi
+ fi
+}
+
+######################################################
+# get folder to use for template.conf files
+#
+get_templateconf()
+{
+ if [ "$DISTRO" = "nodistro" ]; then
+ #for nodistro choice use default sample files from openembedded-core
+ echo ""
+ echo "[WARNING] Using default openembedded template configuration files for '$DISTRO' setting."
+ echo ""
+ _TEMPLATECONF=""
+ else
+ #extract bsp path
+ local distro_path=$(find ${ROOTOE}/$_META_LAYER_ROOT/ -type d \( -name '.git' -o -name '.repo' -o -name 'build*' -o -name 'source*' -o -name 'script*' \) -prune -o -type f -name "$DISTRO.conf" | grep "/distro/$DISTRO.conf" | sed 's|\(.*\)/conf/distro/\(.*\)|\1|')
+ if [ -z "$distro_path" ]; then
+ echo ""
+ echo "[ERROR] No '$DISTRO.conf' file available in $_META_LAYER_ROOT"
+ echo ""
+ return 1
+ fi
+ #make sure path is single
+ if [ "$(echo $distro_path | wc -w)" -gt 1 ]; then
+ echo ""
+ echo "[ERROR] Found multiple '$DISTRO.conf' file in $_META_LAYER_ROOT"
+ echo ""
+ return 1
+ fi
+ #configure _TEMPLATECONF path
+ if [ -f $distro_path/conf/template/bblayers.conf.sample ]; then
+ _TEMPLATECONF=$distro_path/conf/template
+ else
+ echo "[WARNING] default template configuration files not found in $_META_LAYER_ROOT layer: using default ones from openembedded"
+ _TEMPLATECONF=""
+ fi
+ fi
+}
+
+######################################################
+# Check last modified time for bblayers.conf from list of builddir provided and
+# provide builddir that contains the latest bblayers.conf modified
+#
+_default_config_get() {
+ local list=$1
+ TmpFile=$(mktemp)
+ for l in $list
+ do
+ [ -f ${ROOTOE}/$l/conf/bblayers.conf ] && echo $(stat -c %Y ${ROOTOE}/$l/conf/bblayers.conf) $l >> $TmpFile
+ done
+ cat $TmpFile | sort -r | head -n1 | cut -d' ' -f2
+ rm -f $TmpFile
+}
+
+######################################################
+# Init timestamp on bblayers.conf for builddir set
+#
+_default_config_set() {
+ [ -f $BUILDDIR/conf/bblayers.conf ] && touch $BUILDDIR/conf/bblayers.conf
+}
+
+
+######################################################
+# Format DISTRO and MACHINE list from configuration file list applying the specific _FORMAT_PATTERN:
+# <CONFIG-NAME>|<_FORMAT_PATTERN>|<CONFIG-DESCRIPTION>
+#
+_choice_formated_configs() {
+ local choices=$(find ${ROOTOE}/$_META_LAYER_ROOT/ -type d \( -name '.git' -o -name '.repo' -o -name 'build*' -o -name 'source*' -o -name 'script*' \) -prune -o -type f -wholename "*/conf/$1/*.conf" 2>/dev/null | grep ".*/conf/$1/.*\.conf" | sort | uniq)
+
+ for ITEM in $choices; do
+ if [ -z "$(grep '#@DESCRIPTION' $ITEM)" ]; then
+ echo $ITEM | sed 's|^'"${ROOTOE}/$_META_LAYER_ROOT"'/\(.*\)/conf/'"$1"'/\(.*\)\.conf|\2'"${_FORMAT_PATTERN}"'[ERROR] No Description available (\1)|'
+ else
+ grep -H "#@DESCRIPTION" $ITEM | sed 's|^.*/\(.*\)\.conf:#@DESCRIPTION:[ \t]*\(.*$\)|\1'"${_FORMAT_PATTERN}"'\2|'
+ fi
+ done
+ unset ITEM
+}
+
+######################################################
+# Format BUILD_DIR list from applying the specific _FORMAT_PATTERN:
+# <DIR-NAME>|<_FORMAT_PATTERN>|<DISTRO-value and MACHINE-value>
+#
+_choice_formated_dirs() {
+ TmpFile=$(mktemp)
+ for dir in $1
+ do
+ echo "${dir}${_FORMAT_PATTERN}DISTRO is '$(_stoe_config_read ${ROOTOE}/$dir DISTRO)' and MACHINE is '$(_stoe_config_read ${ROOTOE}/$dir MACHINE)'" >> $TmpFile
+ done
+ # Add new build config option
+ echo "NEW${_FORMAT_PATTERN}*** SET NEW DISTRO AND MACHINE BUILD CONFIG ***" >> $TmpFile
+ echo "$(cat $TmpFile)"
+ rm -f $TmpFile
+}
+
+######################################################
+# Make selection for <TARGET> requested from <LISTING> provided using shell or ui choice
+#
+_choice_shell() {
+ local choice_name=$1
+ local choice_list=$2
+ local default_choice=$3
+ #format list to have display aligned on column with '-' separation between name and description
+ local options=$(echo "${choice_list}" | column -t -s "£")
+ #change separator from 'space' to 'end of line' for 'select' command
+ old_IFS=$IFS
+ IFS=$'\n'
+ local i=1
+ unset LAUNCH_MENU_CHOICES
+ for opt in $options; do
+ printf "%3.3s. %s\n" $i $opt
+ LAUNCH_MENU_CHOICES=(${LAUNCH_MENU_CHOICES[@]} $opt)
+ i=$(($i+1))
+ done
+ IFS=$old_IFS
+ # Item selection from list
+ local selection=""
+ # Init default_choice if not already provided
+ [ -z "${default_choice}" ] && default_choice=$(echo ${LAUNCH_MENU_CHOICES[0]} | cut -d' ' -f1)
+ while [ -z "$selection" ]; do
+ echo -n "Which one would you like? [${default_choice}] "
+ read -r -t $READTIMEOUT answer
+ # Check that user has answered before timeout, else break
+ test "$?" -gt "128" && break
+
+ if [ -z "$answer" ]; then
+ selection=${default_choice}
+ break
+ fi
+ if [[ $answer =~ ^[0-9]+$ ]]; then
+ if [ $answer -gt 0 ] && [ $answer -le ${#LAUNCH_MENU_CHOICES[@]} ]; then
+ selection=${LAUNCH_MENU_CHOICES[$(($answer-1))]}
+ break
+ fi
+ fi
+ echo "Invalid choice: $answer"
+ echo "Please use numeric value between '1' and '$(echo "$options" | wc -l)'"
+ done
+ eval ${choice_name}=$(echo $selection | cut -d' ' -f1)
+}
+
+_choice_ui() {
+ local choice_name=$1
+ local choice_list=$2
+ local default_choice=$3
+ local target=""
+ local _help_display=true
+ #change separator from 'space' to 'end of line' to get full line
+ old_IFS=$IFS
+ IFS=$'\n'
+ for ITEM in ${choice_list}; do
+ local target_name=$(echo $ITEM | awk -F''"${_FORMAT_PATTERN}"'' '{print $1}')
+ local target_desc=$(echo $ITEM | awk -F''"${_FORMAT_PATTERN}"'' '{print $NF}')
+ local target_stat="OFF"
+ # Set selection ON for default_choice
+ [ "$target_name" = "$default_choice" ] && target_stat="ON"
+ TARGETTABLE+=($target_name "$target_desc" $target_stat)
+ done
+ IFS=$old_IFS
+ while [[ -z "$target" ]]
+ do
+ target=$(${UI_CMD} --title "Available ${choice_name}" --radiolist "Please choose a ${choice_name}" 0 0 0 "${TARGETTABLE[@]}" 3>&1 1>&2 2>&3)
+ test -z $target || break
+ if $_help_display; then
+ #display dialog box to provide some help to user
+ ${UI_CMD} --title "How to select ${choice_name}" --msgbox "Keyboard usage:\n\n'ENTER' to validate\n'SPACE' to select\n 'TAB' to navigate" 0 0
+ _help_display=false
+ else
+ break
+ fi
+ done
+ unset TARGETTABLE
+ unset ITEM
+ eval ${choice_name}=$target
+}
+
+choice() {
+ local __TARGET=$1
+ local choices="$2"
+ local default_choice=$3
+ echo "[$__TARGET configuration]"
+ if [[ $(echo "$choices" | wc -l) -eq 1 ]]; then
+ eval $__TARGET=$(echo $choices | awk -F''"${_FORMAT_PATTERN}"'' '{print $1}')
+ else
+ if ! [[ -z "$DISPLAY" ]] && ! [[ -z "${UI_CMD}" ]]; then
+ _choice_ui $__TARGET "$choices" $default_choice
+ else
+ _choice_shell $__TARGET "$choices" $default_choice
+ fi
+ fi
+ echo "Selected $__TARGET: $(eval echo \$$__TARGET)"
+ echo ""
+}
+
+######################################################
+# Check if current HOST is one of the Linux Distrib Release supported
+#
+_stoe_distrib_check() {
+ # Init UbuntuRelease text
+ UbuntuReleaseFile=$(mktemp)
+ # Set default return value
+ local return_value=0
+ # Set lsb-release file
+ local lsb_release_file=/etc/lsb-release
+ # Init host info
+ local host_distrib="Not checked"
+ local host_release="Not checked"
+ if [ -f $lsb_release_file ]; then
+ # Check for host Linux Distrib
+ host_distrib=$(grep '^DISTRIB_ID=' $lsb_release_file | cut -d'=' -f2)
+ if [ "$host_distrib" != "${_SUPPORTED_LINUX_DISTRIB}" ]; then
+ echo "[WARNING] Not supported Linux Distrib detected in $lsb_release_file file" > $UbuntuReleaseFile
+ echo "[WARNING] ($host_distrib)" >> $UbuntuReleaseFile
+ return_value=1
+ else
+ # Check for host Linux Distrib Release
+ host_release=$(grep '^DISTRIB_RELEASE=' $lsb_release_file | cut -d'=' -f2)
+ # Init release support info
+ local supported_release="no"
+ for release in ${_SUPPORTED_UBUNTU_RELEASE}
+ do
+ [ "$host_release" = "$release" ] && supported_release="yes"
+ done
+ if [ "$supported_release" = "no" ]; then
+ echo "[WARNING] Not supported ${_SUPPORTED_LINUX_DISTRIB} Release detected in $lsb_release_file file" > $UbuntuReleaseFile
+ echo "[WARNING] ($host_release)" >> $UbuntuReleaseFile
+ return_value=1
+ fi
+ fi
+ else
+ echo "[WARNING] Skip checking for Linux Distrib Release support." > $UbuntuReleaseFile
+ echo "[WARNING] (missing $lsb_release_file file on host)" >> $UbuntuReleaseFile
+ return_value=1
+ fi
+ # Display host checking info
+ echo "Linux Distrib: $host_distrib"
+ echo "Linux Release: $host_release"
+ echo ""
+ # Check for user acknowledgment
+ if [ "$return_value" -eq 1 ]; then
+ # Amend warning message with default Linux Distrib support and advice
+ echo "" >> $UbuntuReleaseFile
+ echo "ST recommands to use one of the following distributions (validated by ST)" >> $UbuntuReleaseFile
+ echo " DISTRIB: ${_SUPPORTED_LINUX_DISTRIB}" >> $UbuntuReleaseFile
+ echo " RELEASE: ${_SUPPORTED_UBUNTU_RELEASE}" >> $UbuntuReleaseFile
+ echo "Feel free to update your distribution, or to ignore the WARNING (at your risk)..." >> $UbuntuReleaseFile
+ # Select mode to dialogue with user
+ if ! [[ -z "$DISPLAY" ]] && ! [[ -z "${UI_CMD}" ]]; then
+ # UI mode (through dialogue boxes)
+ if (${UI_CMD} --title "UBUNTU RELEASE SUPPORT" --yesno "$(cat $UbuntuReleaseFile)" 0 0 --yes-button "IGNORE WARNING" --no-button "EXIT"); then
+ return_value=0
+ fi
+ else
+ # Default console mode
+ local answer=
+ local wrong_answer=0
+ cat $UbuntuReleaseFile
+ while [ -z "$answer" ] && [ "$wrong_answer" -lt "$TRIALMAX" ]; do
+ echo -n "Would you ignore this warning ? (y/n) "
+ read -r -t $READTIMEOUT answer
+ if [ "$?" -gt "128" ]; then
+ echo
+ echo "[WARNING] Timeout reached"
+ echo "[WARNING] Default answer to 'no'."
+ echo
+ answer="no"
+ elif (echo -n $answer | grep -q -e "^[yY][a-zA-Z]*$"); then
+ answer="yes"
+ elif (echo -n $answer | grep -q -e "^[nN][a-zA-Z]*$"); then
+ answer="no"
+ else
+ answer=
+ wrong_answer=$((wrong_answer+1))
+ if [ "$wrong_answer" -eq "$TRIALMAX" ]; then
+ echo
+ echo "[WARNING] Maximum trials reached"
+ echo "[WARNING] Default answer to 'no'."
+ echo
+ answer="no"
+ fi
+ fi
+ done
+ # Convert answer to expected return value
+ if [ "$answer" == "yes" ]; then
+ return_value=0
+ fi
+ fi
+ fi
+ # Remove temporary file
+ rm -f $UbuntuReleaseFile
+ return $return_value
+}
+
+######################################################
+# Since this script is sourced, be careful not to pollute
+# caller's environment with temp variables.
+#
+_stoe_unset() {
+ unset BUILD_DIR
+ unset DISTRO
+ unset DISTRO_INIT
+ unset MACHINE
+ unset MACHINE_INIT
+ unset _DL_CACHEPREFIX
+ unset _SSTATE_CACHEPREFIX
+ unset _NCPU
+ unset _SITECONFSAMPLE_PATH
+ unset _FORCE_RECONF
+ unset _ENABLE_UI
+ unset _INIT
+ unset _BUILDSYSTEM
+ unset _QUIET
+ unset UI_CMD
+ unset _TEMPLATECONF
+ unset _DISTRO_CODENAME
+ unset _EULA_ACCEPT
+ unset _EULA_ENABLE
+ unset _SUPPORTED_LINUX_DISTRIB
+ unset _SUPPORTED_UBUNTU_RELEASE
+ unset BSP_DEPENDENCY
+ # Clean env from unwanted functions
+ unset -f choice
+ unset -f _choice_ui
+ unset -f _choice_shell
+ unset -f _verify_env
+ unset -f _choice_formated_dirs
+ unset -f _choice_formated_configs
+ unset -f get_templateconf
+ unset -f conf_bblayerconf
+ unset -f conf_localconf
+ unset -f conf_siteconf
+ unset -f conf_notes
+ unset -f _stoe_set_env_init
+ unset -f stoe_set_env
+ unset -f _default_config_get
+ unset -f _default_config_set
+ unset -f get_distrocodename
+ unset -f eula_check
+ unset -f eula_askuser
+ unset -f _stoe_distrib_check
+ # Delete File
+ rm -f ${LISTDIR}
+}
+
+######################################################
+# Check if script is sourced as expected
+#
+_verify_env() {
+ local __resultvar=$1
+ if [ "$0" = "$BASH_SOURCE" ]; then
+ echo "###################################"
+ echo "[ERROR] YOU MUST SOURCE the script"
+ echo "###################################"
+ if [[ "$__resultvar" ]]; then
+ eval $__resultvar="ERROR_SOURCE"
+ fi
+ return
+ fi
+ # check that we are not root!
+ if [ "$(whoami)" = "root" ]; then
+ echo -e "\n[ERROR] do not use the BSP as root. Exiting..."
+ if [[ "$__resultvar" ]]; then
+ eval $__resultvar="ERROR_ROOT"
+ fi
+ return
+ fi
+ # check that we are where we think we are!
+ local oe_tmp_pwd=$(pwd)
+ # need to take care of build system available
+ if [[ ! -d $oe_tmp_pwd/layers/openembedded-core ]] && [[ ! -d $oe_tmp_pwd/layers/poky ]]; then
+ echo "PLEASE launch the envsetup script at root tree of your oe sdk"
+ echo ""
+ local oe_tmp_root=$oe_tmp_pwd
+ while [ 1 ];
+ do
+ oe_tmp_root=$(dirname $oe_tmp_root)
+ if [ "$oe_tmp_root" == "/" ]; then
+ echo "[WARNING]: you try to launch the script outside oe sdk tree"
+ break;
+ fi
+ if [[ -d $oe_tmp_root/layers/openembedded-core ]] || [[ -d $oe_tmp_root/layers/poky ]]; then
+ echo "Normally at this location: $oe_tmp_root"
+ break;
+ fi
+ done
+ if [[ "$__resultvar" ]]; then
+ eval $__resultvar="ERROR_OE"
+ fi
+ return
+ else
+ # Fix build system to use for init: default would be openembedded-core one
+ [[ -d $oe_tmp_pwd/layers/poky ]] && _BUILDSYSTEM=layers/poky
+ [[ -d $oe_tmp_pwd/layers/openembedded-core ]] && _BUILDSYSTEM=layers/openembedded-core
+ fi
+ if [[ "$__resultvar" ]]; then
+ eval $__resultvar="NOERROR"
+ fi
+}
+
+######################################################
+# Main
+# --
+#
+
+#----------------------------------------------
+# Make sure script has been sourced
+#
+_verify_env ret
+case $ret in
+ ERROR_OE | ERROR_ROOT | ERROR_SOURCE)
+ if [ "$0" != "$BASH_SOURCE" ]; then
+ return 2
+ else
+ exit 2
+ fi
+ ;;
+ *)
+ ;;
+esac
+
+# Init parameters
+_ENABLE_UI=1
+READTIMEOUT=${READTIMEOUT:-60}
+TRIALMAX=${TRIALMAX:-100}
+
+#----------------------------------------------
+# parsing options
+#
+while test $# != 0
+do
+ case "$1" in
+ --help)
+ stoe_help
+ _stoe_utilities
+ return 1
+ ;;
+ --quiet)
+ _QUIET=1
+ ;;
+ --reset)
+ _FORCE_RECONF=1
+ _INIT=0
+ ;;
+ --no-ui)
+ _ENABLE_UI=0
+ ;;
+ -*)
+ echo "Wrong parameter: $1"
+ return 1
+ ;;
+ *)
+ #change buildir directory
+ if ! [[ $1 =~ ^build.* ]]; then
+ echo "[ERROR] '$1' : please provide BUILD_DIR with 'build' prefix."
+ return 1
+ fi
+ #we want BUILD_DIR without any '/' at the end
+ BUILD_DIR=$(echo $1 | sed 's|[/]*$||')
+ ;;
+ esac
+ shift
+done
+
+#----------------------------------------------
+# Init env variable
+#
+_stoe_set_env_init
+
+#----------------------------------------------
+# Check if Linux Distrib is supported
+#
+echo "[HOST DISTRIB check]"
+_stoe_distrib_check
+test "$?" == "1" && { echo "Check aborted: exiting now..."; _stoe_unset; return 1; }
+
+#----------------------------------------------
+# Init BUILD_DIR variable
+#
+if [ -z "${BUILD_DIR}" ] && ! [ -z "$DISTRO" ] && ! [ -z "$MACHINE" ]; then
+ # In case DISTRO and MACHINE are provided use them to init BUILD_DIR
+ BUILD_DIR="build-${DISTRO//-}-$MACHINE"
+fi
+
+if [ -z "${BUILD_DIR}" ]; then
+ # Get existing BUILD_DIR list from baseline
+ LISTDIR=$(mktemp)
+ for l in $(find ${ROOTOE} -maxdepth 1 -wholename "*/build*"); do
+ test -f ${l}/conf/local.conf && echo ${l#*${ROOTOE}/} >> ${LISTDIR}
+ done
+ # Select any existing BUILD_DIR from list
+ if [ -s ${LISTDIR} ]; then
+ choice BUILD_DIR "$(_choice_formated_dirs "$(cat ${LISTDIR} | sort)")" $(_default_config_get "$(cat ${LISTDIR} | sort)")
+ [ -z "${BUILD_DIR}" ] && { echo "Selection escaped: exiting now..."; _stoe_unset; return 1; }
+ fi
+ # Reset BUILD_DIR in case for new config choice
+ test "${BUILD_DIR}" == "NEW" && BUILD_DIR=""
+else
+ # Check if configuration files exist to force or not INIT
+ test -f ${ROOTOE}/${BUILD_DIR}/conf/bblayers.conf || _INIT=1
+ test -f ${ROOTOE}/${BUILD_DIR}/conf/local.conf || _INIT=1
+fi
+
+if [[ $_INIT -eq 1 ]] || [[ -z "${BUILD_DIR}" ]]; then
+ # There is no available config in baseline: force init from scratch
+ _INIT=1
+
+ # Set DISTRO
+ if [ -z "$DISTRO" ]; then
+ DISTRO_CHOICES=$(_choice_formated_configs distro)
+ test "$?" == "1" && { echo "$DISTRO_CHOICES"; _stoe_unset; return 1; }
+ # Add nodistro option
+ DISTRO_CHOICES=$(echo -e "$DISTRO_CHOICES\nnodistro${_FORMAT_PATTERN}*** DEFAULT OPENEMBEDDED SETTING : DISTRO is not defined ***")
+ choice DISTRO "$DISTRO_CHOICES"
+ [ -z "$DISTRO" ] && { echo "Selection escaped: exiting now..."; _stoe_unset; return 1; }
+ fi
+
+ # Set MACHINE
+ if [ -z "$MACHINE" ]; then
+ MACHINE_CHOICES=$(_choice_formated_configs machine)
+ test "$?" == "1" && { echo "$MACHINE_CHOICES"; _stoe_unset; return 1; }
+ choice MACHINE "$MACHINE_CHOICES"
+ [ -z "$MACHINE" ] && { echo "Selection escaped: exiting now..."; _stoe_unset; return 1; }
+ fi
+
+ # Init BUILD_DIR if not yet set
+ test -z "${BUILD_DIR}" && BUILD_DIR="build-${DISTRO//-}-$MACHINE"
+
+ # Check if BUILD_DIR already exists to use previous config (i.e. set _INIT to 0)
+ test -f ${ROOTOE}/${BUILD_DIR}/conf/bblayers.conf && _INIT=0
+ test -f ${ROOTOE}/${BUILD_DIR}/conf/local.conf && _INIT=0
+
+else
+ # Get DISTRO and MACHINE from configuration file
+ DISTRO_INIT=$(_stoe_config_read ${ROOTOE}/${BUILD_DIR} DISTRO)
+ MACHINE_INIT=$(_stoe_config_read ${ROOTOE}/${BUILD_DIR} MACHINE)
+
+ # If DISTRO value is not set in conf file, then default to nodistro
+ [[ ${DISTRO_INIT} =~ \< ]] && DISTRO_INIT="nodistro"
+
+ # Set DISTRO
+ if [ -z "$DISTRO" ]; then
+ DISTRO=${DISTRO_INIT}
+ elif [ "$DISTRO" != "${DISTRO_INIT}" ]; then
+ # User has defined a wrong DISTRO for current BUILD_DIR configuration
+ echo "[ERROR] DISTRO $DISTRO does not match "${DISTRO_INIT}" already set in ${BUILD_DIR}"
+ _stoe_unset
+ return 1
+ fi
+
+ # Set MACHINE
+ if [ -z "$MACHINE" ]; then
+ MACHINE=${MACHINE_INIT}
+ elif [ "$MACHINE" != "${MACHINE_INIT}" ]; then
+ # User has defined a wrong MACHINE for current BUILD_DIR configuration
+ echo "[ERROR] MACHINE $MACHINE does not match "${MACHINE_INIT}" already set in ${BUILD_DIR}"
+ _stoe_unset
+ return 1
+ fi
+fi
+
+#----------------------------------------------
+# Init baseline for full INIT if required
+#
+if [[ $_FORCE_RECONF -eq 1 ]] && [[ $_INIT -eq 0 ]]; then
+ echo ""
+ echo "[Removing current config from ${ROOTOE}/${BUILD_DIR}/conf]"
+ rm -fv ${ROOTOE}/${BUILD_DIR}/conf/*.conf ${ROOTOE}/${BUILD_DIR}/conf/*.txt
+ echo ""
+ # Force init to generate configuration files
+ _INIT=1
+fi
+
+#----------------------------------------------
+# Standard Openembedded init
+#
+echo -en "[source $_BUILDSYSTEM/oe-init-build-env]"
+[[ $_INIT -eq 1 ]] && echo "[from nothing]"
+[[ $_INIT -eq 0 ]] && echo "[with previous config]"
+get_templateconf
+test "$?" == "1" && { _stoe_unset; return 1; }
+TEMPLATECONF=${_TEMPLATECONF} source ${ROOTOE}/$_BUILDSYSTEM/oe-init-build-env ${BUILD_DIR} > /dev/null
+test "$?" == "1" && { _stoe_unset; return 1; }
+
+#----------------------------------------------
+# Init ST DISTRO CODE NAME to use for DL_DIR and SSTATE_DIR path
+#
+get_distrocodename
+test "$?" == "1" && { rm -rf $BUILDDIR/conf/*; _stoe_unset; return 1; }
+
+#----------------------------------------------
+# Handle EULA acceptance for ST configurations
+#
+if [[ $_INIT -eq 1 ]]; then
+ echo
+ echo "[EULA configuration]"
+ eula_check
+ test "$?" == "1" && { rm -rf $BUILDDIR/conf/*; _stoe_unset; return 1; }
+fi
+
+#----------------------------------------------
+# Apply specific ST configurations
+#
+if [[ $_INIT -eq 1 ]]; then
+ echo
+ echo "[Configure *.conf files]"
+ # Configure site.conf with specific settings
+ conf_siteconf
+ # Configure local.conf with specific settings
+ conf_localconf
+ # Update bblayer.conf with specific machine bsp layer path
+ conf_bblayerconf
+ # Copy specific 'conf-notes.txt' file from templateconf to BUILDDIR
+ conf_notes
+fi
+
+#----------------------------------------------
+# Init ST environment variables
+#
+stoe_set_env
+
+#----------------------------------------------
+# Display when no quiet mode required
+#
+if ! [[ $_QUIET -eq 1 ]]; then
+ # Display current configs
+ stoe_config_summary $BUILDDIR
+
+ # Display available images
+ if [ -f $BUILDDIR/conf/conf-notes.txt ]; then
+ cat $BUILDDIR/conf/conf-notes.txt
+ else
+ stoe_list_images ${ROOTOE}/${_META_LAYER_ROOT} NOERR FILTER
+ test "$?" == "1" && { _stoe_unset; return 1; }
+ fi
+ echo ""
+ echo "You can now run 'bitbake <image>'"
+ echo ""
+fi
+
+#----------------------------------------------
+# Init timestamp for default builddir choice
+#
+_default_config_set
+
+#----------------------------------------------
+# Clear user's environment from temporary variables
+#
+_stoe_unset