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authorStefan Riedmueller <s.riedmueller@phytec.de>2019-07-15 09:14:19 +0200
committerStefan Müller-Klieser <s.mueller-klieser@phytec.de>2019-07-17 15:21:27 +0200
commit3e26f683def8827a6b05d65998c292d153d74646 (patch)
tree30b45b9cf2108d2e70b7a1062f6960e108c27b7c
parent9497584735fda4fa084d2dcf032e65e65439d9ab (diff)
downloadmeta-phytec-3e26f683def8827a6b05d65998c292d153d74646.tar.bz2
meta-phytec-3e26f683def8827a6b05d65998c292d153d74646.zip
kernel: linux-mainline: imx6: Update recipe version to v4.14.126-phy1
Changes from v4.14.78-phy2 to v4.14.126-phy1: ARM: dts: imx6q: Increase SOC voltage for low frequencies ARM: dts: peb-eval-01: Fix used led node names arm: dts: am335x-regor: Fix user-led setup UPSTREAM: ARM: dts: imx6ull: update vdd_soc voltage for 900MHz operating point ARM: dts: imx6ull: segin: Add model and compatible ARM: dts: imx6ull: phycore: Add model and compatible ARM: dts: imx6ul: segin: Unify license and model description ARM: dts: imx6ul: phytec: Do not use CSI on low cost Segin ARM: dts: Makefile: Add missing entry for phyBOARD-Segin with eMMC ARM: dts: imx6ull: segin: Fix uart5 pinmuxing ARM: dts: imx6ul: segin: Reduce eth drive strength NXP: MLK-11284 ARM: ERRATA: Add ARM/MP: 814220 SW workaround media: mt9p031: Fix pause_restart handling ... Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Norbert Wesp <n.wesp@phytec.de>
-rw-r--r--recipes-kernel/linux/linux-mainline_4.14.126-phy1.bb (renamed from recipes-kernel/linux/linux-mainline_4.14.78-phy2.bb)2
1 files changed, 1 insertions, 1 deletions
diff --git a/recipes-kernel/linux/linux-mainline_4.14.78-phy2.bb b/recipes-kernel/linux/linux-mainline_4.14.126-phy1.bb
index 85f678d..95452eb 100644
--- a/recipes-kernel/linux/linux-mainline_4.14.78-phy2.bb
+++ b/recipes-kernel/linux/linux-mainline_4.14.126-phy1.bb
@@ -12,7 +12,7 @@ PR = "${INC_PR}.0"
# NOTE: PV must be in the format "x.y.z-.*". It cannot begin with a 'v'.
# NOTE: Keep version in filename in sync with commit id!
-SRCREV = "0f02caef585b6c60fbfa70de14e63277e69c1f27"
+SRCREV = "a98a84737814071e544b522af867776350c7a435"
S = "${WORKDIR}/git"